Signal Integrity Engineer Manager in Silicon Valley

Posted: 3/25/2007

Signal Integrity Engineer Manager

Managing a team of 12-20 individual Signal Integrity Engineers

Responsibilities

• Perform system level signal integrity and timing analysis on boards, packages, ASICs and FPGAs.

• Management experience required
• Familiar with timing (setup/hold board timing analysis and clock design.
• Proficient with board level reflection, xtalk, ground bounce, bypassing techniques for power/ground noise reduction, termination techniques for reflection noise control, on chip SI including core noise modelling, on chip crosstalk, I/O selection, chip pinout assignment, package selection and pinout assignment, PWB cross-sec ion design/tradeoff, serdes channel S21 channel analysis.
• Proficient with 2-D/3-D cad tools, hspice, matlab, SpecctraQuest
• Proficient in the lab with oscilliscopes, Time Domain Reflectometers, Vector Network Analyzers, Spectrum Analyzers, , skew/jitter/phase noise measurements, phase lock loop bandwidth sensitivity to noise.
• Good lab debug skills.
• Excellent oral and written communication skills.
• Team player, willing to take on a variety of projects, good listening skills, self motivator.

Contact:
Patrick Jordan
Executive Recruiter
Nelson Human Resource Solutions Group
Voice: 707.939.4012 Mobile: 707.321.2790 Fax: 707.935.6124 Website: www.nelsonhr.com Email: pjordan@nelsonhe_pjordan@nelsonhr.com

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