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Editorial--Transition to Online Peer Review

J. P. Krusius

[p. 130]

CONTRIBUTIONS FROM THE 49TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE

Foreword

M. Swaminathan

[p. 131]

Sensitivity Analysis of Multiconductor Transmission Lines and Optimization for High-Speed Interconnect Circuit Design

C. Jiao, A. C. Cangellaris, A. M. Yaghmour, J. L. Prince

[p. 132]

Pole-Residue Formulation for Transient Simulation of High-Frequency Interconnects Using Householder LS Curve-Fitting Techniques

M. Elzinga, K. L. Virga, L. Zhao, and J. L. Prince

[p. 142]

An Efficient Crosstalk Parameter Extraction Method For High Speed Interconnection Lines

M. Sung, W. Ryu, H. Kim, J. Kim, and J. Kim

[p. 148]

Modeling the Power and Ground Effects of BGA Packages

M. F. Caggiano, B. DelGiudice, K. J. Tornquist

[p. 156]

ADDITIONAL CONTRIBUTIONS FROM THE 49TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE

Foreword

J. P. Krusius and L. S. Watkins

[p. 164]

High Coupling Optical Design for Laser Diodes with Large Aspect Ratio

S.-Y. Huang, C. E. Gaebe, K. A. Miller, G. T. Wiand, and T. S. Stakelon

[p. 165]

Spectroscopic Measurement of Mounting-Induced Strain in Optoelectronic Devices

A. Bärwolff, J. W. Tomm, R. Müller, S. Wei\beta, M. Hutter, H. Oppermann, and H. Reichl

[p. 170]

2 Gbit/s Small Form Factor Fiber-Optic Transceiver for Single Mode Optical Fiber

Y. Sunaga, R. Takahashi, T. Tokoro, and M. Kobayashi

[p. 176]

Agilent Technologies' Singlemode Small Form Factor (SFF) Module Incorporates Micromachined Silicon, Automated Passive Alignment, and Non-Hermetic Packaging to Enable the Next Generation of Low-Cost Fiber Optic Transceivers

M. Owen

[p. 182]

Performance Comparison of Small Form Factor Fiber Optic Connectors

J. M. Trewhella, C. M. DeCusatis, and J. Fox

[p. 188]

CONTRIBUTIONS FROM TC-18 WAFER SCALE PACKAGING

Foreword

P. Garrou

[p. 197]

Wafer Level Chip Scale Packaging (WL-CSP): An Overview

P. Garrou

[p. 198]

A Minimal CSP

G. A. Rinne, J. D. Walling, and J. D. Mis

[p. 206]

Ultrathin Wafer Level Chip Size Package

A. Badihi

[p. 212]

Super

CSP

T. Kawahara

[p. 215]

Ultra

CSP^TM--A Wafer Level Package

P. Elenius, S. Barrett, T. Goodman

[p. 220]

MicroSMD--A Wafer Level Chip Scale Package

N. Kelkar, R. Mathew, H. Takiar, and L. Nguyen

[p. 227]

Wafer Level Chip Size package (WL-CSP)

M. Töpper, S. Fehlberg, K. Scherpinski, C. Karduck, V. Glaw, K. Heinricht, P. Coskina, O. Ehrmann, and H. Reichl

[p. 233]

Improved Thermal Fatigue Reliability for Flip Chip Assemblies Using Redistribution Techniques

B. Vandevelde and E. Beyne

[p. 239]

Wafer Level Chip Scale Packaging: Benefits for Integrated Passive Devices

H. M. Clearfield, J. L. Young, S. D. Wijeyesekera, and E. A. Logan

[p. 247]

CONTRIBUTED PAPERS

Development of Three-Dimensional Memory Die-Stack Packages Using Polymer Insulated Sidewall Technique

H. S. Ko, J. S. Kim, H. G. Yoon, S. Y. Jang, S. D. Cho and K. W. Paik

[p. 252]

A Novel Robust and Low Cost Stack Chips Package and Its Thermal Performance

S.-J. Cho, S.-W. Park, M.-G. Park, and D.-H. Kim

[p. 257]

Application of the Taguchi Method to Chip Scale Package (CSP) Design

A. Mertol

[p. 266]

Effect of Randomness of Cu-Sn Intermetallic Compound Layer Thickness on Reliability of Surface Mount Solder Joints

W. Huang, O. A. Palusinski, and D. L. Dietrich

[p. 277]

A Comparison of Hourly Versus Daily Testing Methods for Evaluating the Reliability of Water Soluble Fluxes

W. J. Ready and L. J. Turbini

[p. 285]

A Study of the High Frequency Performance of Thin Film Capacitors for Electronic Packaging

K. Y. Chen, W. D. Brown, L. W. Schaper, S. S. Ang, and H. A. Naseem

[p. 293]

New Simultaneous Switching Noise Analysis and Modeling for High-Speed and High Density CMOS IC Package Design

Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and O.-K. Kwon

[p. 303]

Factors Influencing the Permittivity of Polymer/Ceramic Composites for Embedded Capacitors

S. Ogitani, S. A. Bidstrup-Allen, and P. A. Kohl

[p. 313]

Passively Aligned LD/PD Array Submodules by Using Micro-Capillaries

H. Takahara, N. Tanaka, and Y. Arai

[p. 323]

ANNOUNCEMENTS

Call for Papers--Ninth Topical Meeting on Electrical Performance of Electronic Packaging

[p. 328]

1999 List of Reviewers

[p. 335]