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IEEE Transactions on
Advanced Packaging

A PUBLICATION OF THE IEEE COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY SOCIETY

May, 2001, Volume 24, Number 02

See IEEE Xplore to download PDF copies (available service for subscribers).

Foreword: Electrical Design Papers from the 2000 Electronic Components and Technology Conference
Page(s): 119 -119


Rules for robust generation of accurate reduced-order models for high-speed coupled interconnections
Cangellaris, A.C.; Igarashi, M.
Page(s): 120 -125


An all-purpose dispersive multiconductor interconnect model compatible with PRIMA
Pasha, S.; Cangellaris, A.C.; Prince, J.L.
Page(s): 126 -131


Modeling of simultaneous switching noise in high speed systems
Sungjun Chun; Swaminathan, M.; Smith, L.D.; Srinivasan, J.; Zhang Jin; Iyer, M.K.
Page(s): 132 -142


Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation
Jun Fan; Hao Shi; Orlandi, A.; Knighten, J.L.; Drewniak, J.L.
Page(s): 143 -157


An overview of solder bump shape prediction algorithms with validations
Kuo-Ning Chiang; Chang-An Yuan
Page(s): 158 -162


Nondestructive methodology for standoff height measurement of flip chip on flex (FCOF) by SAM
Tang, C.W.; Chan, Y.C.; Hung, K.C.; Webb, D.P.
Page(s): 163 -168


Multichip module photovoltaic miniarrays
Ortego, P.R.; Bermejo, S.; Castaner, L.M.
Page(s): 169 -174


Electron beam enhanced multilayering and planarization in preimidized polyimides
Manepalli, R.; Kovach, D.J.; Farnsworth, K.; Chiniwalla, P.; Dusch, B.; Bidstrup-Allen, S.A.; Kohl, P.A.
Page(s): 175 -183


Analysis of the bounces on the power/ground plane structures by planar circuit model and APA-E algorithm
Xiaoping Yang; Zhengfan Li; Junfa Mao
Page(s): 184 -190


Time domain modeling of lossy interconnects
Svensson, C.; Dermer, G.H.
Page(s): 191 -196


Effect of intermetallic compounds on vibration fatigue of /spl mu/BGA solder joint
Tu, P.L.; Chan, Y.C.; Lai, J.K.L.
Page(s): 197 -205


Chip-scale packaging of power devices and its application in integrated power electronics modules
Xingsheng Liu; Xiukuan Jing; Guo-Quan Lu
Page(s): 206 -215


Failure analysis and stress simulation in small multichip BGAs
Moore, T.D.; Jarvis, J.L.
Page(s): 216 -223


Correction to "lossy power distribution networks with thin dielectric layers and/or thin conductive layers"
Novak, I.; Smith, L.; Roy, T.; Anderson, R.
Page(s): 224 -224


Associate editors, guest editors, and reviewers
Page(s): 225 -226



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