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IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging

November 1996, Volume 19, Issue 04

REGULAR PAPERS

Multichip Modules

Packaging Alternatives to Large Silicon Chips: Tiled Silicon on MCM and PWB Substrates

A. G. George, J. P. Krusius, and R. F. Granitz

Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology

M. B. Kleiner, S. A. Kühn, P. Ramm, and W. Weber

Performance Modeling of the Interconnect Structure of a Three-Dimensional Integrated RISC Processor/Cache System

S. A. Kühn, M. B. Kleiner, P. Ramm, and W. Weber

Chip Attachment and Interconnects

Solder Joint Reliability of Flip Chip and Plastic Ball Grid Array Assemblies Under Thermal, Mechanical, and Vibrational Conditions

J. H. Lau

Low-Cost Flip-Chip on Board

A. F. J. Baggerman, J. F. J. M. Caers, J. J. Wondergem, and A. G. Wagemans

Approaching a Uniform Bump Height of the Electroplated Solder Bumps on a Silicon Wafer

K.-L. Lin and S.-Y. Chang

A New Anisotropic Conductive Film with Arrayed Conductive Particles

K. Ishibashi and J. Kimura

Optoelectronics Packaging

Laser Weldability Analysis of High-Speed Optical Transmission Device Packaging

M. K. Song, S. G. Kang, N. Hwang, H. T. Lee, S. S. Park, and K. E. Pyun

Defect Formation Mechanisms in Laser Welding Techniques for Semiconductor Laser Packaging

W.-H. Cheng, W.-H. Wang, and J.-C. Chen

Design and Electrical Modeling

Extraction of the Capacitance Matrix of Multiconductor Interconnection Lines for High-Speed IC System Design

S.-P. Luo and Z.-F. Li

Application of Path Integrals in Modeling Transmission Line Loss

L. M. Rubin

Computing Inductive Noise of CMOS Drivers

A. J. Rainal

VLSI Interconnect Design Automation Using Quantitative and Symbolic Techniques

T. Simunic, J. W. Rozenblit, and J. R. Brews

1996 INDEX

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