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IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging

February 1998, Volume 21, Number 01


Editorial
J. P. Krusius

[p. 1]


REGULAR PAPERS

3-D Packaging and Multichip Modules

A Review of 3-D Packaging Technology
S. F. Al-sarawi, D. Abbott, and P. D. Franzon

[p. 2]

Three-Dimensional Memory Module
N. Takahashi, N. Senba, Y. Shimada, I. Morisaki, and K. Tokuno

[p. 15]

A High Performance MCM-D/C Application
E. D. Perfecto, H. P. Longworth, R. A. Sherif, M. J. Ellsworth, and R. Yu, Jr.

[p. 20]

Single-Chip Packaging

Molded Chip Scale Package for High Pin Count
S. Baba, Y. Tomita, M. Matsuo, H. Matsushima, N. Ueda, and O. Nakagawa

[p. 28]

Electrical Design of a Cost-Effective Thermal Enhanced Plastic Ball Grid Array Package--NuBGA
J. H. Lau and T.-Y. Chou

[p. 35]

New Design for a Lead Frame Used for High Pin Counts and High-Power LSI Package
M. Mita, S. Takagi, T. Kumakura, K. Yamaguchi, and H. Tanaka

[p. 43]

Materials, Processes, and Substrates

Thermosonic Flip-Chip Bonding Using Longitudinal Ultrasonic Vibration
Q. Tan, W. Zhang, B. Schaible, L. J. Bond, T. H. Ju, and Y. C. Lee

[p. 53]

Material Interactions of Solder Bumps Produced with Fluxless Wave Soldering
K.-L. Lin and W.-H. Chao

[p. 59]

A Three-Dimensional Modeling of Wire Sweep Incorporating Resin Cure
J. H. Wu, A. A. O. Tay, K. S. Yeo, and T. B. Lim

[p. 65]

Multicriteria Decision Making in Design of Printed Wire Boards
Y. Tokat, O. A. Palusinski, and F. Szidarovszky

[p. 73]

Failure Modes and Models

Investigation of Interfacial Fracture Behavior of a Flip-Chip Package Under a Constant Concentrated Load
J. Wang, M. Lu, D. Zou, and S. Liu

[p. 79]

Thermomechanical Analysis in Electronic Packaging with Unified Constitutive Model for Materials and Joints
C. S. Desai, C. Basaran, T. Dishongh, and J. L. Prince

[p. 87]

Electrical Performance of Packaging

Numerical Modeling of a Clock Distribution Network for a Superconducting Multichip Module
P. Vichot, J. A. Mix, Z. Schoenborn, J. Dunn, and M. Piket-May

[p. 98]

Efficient Transient Simulation of High-Speed Interconnects Characterized by Sampled Data
W. T. Beyene and J. E. Schutt-Aine

[p. 105]


IEEE Copyright Form
[p. 119]


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