Getting Copies of these Papers:
Subscribers to this Transactions (and subscribers to XPLORE/IEL/MDL) may freely download the PDFs of any of these papers, at the XPLORE On-Line Library. Guests may access abstract/citation records free of charge.


IEEE Transactions on Semiconductor Manufacturing


May 1996, Volume 9, Issue 2


Editorial
G. Cheek


PAPERS

Benchmarking Semiconductor Manufacturing
R. C. Leachman and D. A. Hodges

Computer-Aided Phase Shift Mask Design with Reduced Complexity
Y. Liu, A. Zakhor, and M. Zuniga

Methods for Measurement of Development Parameters in the Manufacturing Line for Use in Photolithography Modeling
K. P. Fahey

A Control System for Photolithographic Sequences
S. Leang, S.-Y. Ma, J. Thomson, B. J. Bombay, and C. J. Spanos

Control of Photoresist Properties: A Kalman Filter Based Approach
E. Palmer, W. Ren, C. J. Spanos, and K. Poolla

An Efficient Method for Determining Threshold Voltage, Series Resistance and Effective Geometry of MOS Transistorsk
P. R. Karlsson and K. O. Jeppson

A Genetic Algorithm for Low Variance Control in Semiconductor Device Manufacturing: Some Early Results
E. A. Rietman and R. C. Frye

Plasma Enhanced
In Situ Chamber Cleaning Evaluated by Extracted-Plasma-Parameter Analysis
K. Ino, I. Natori, A. Ichikawa, R. N. Vrtis, and T. Ohmi

Etching of AC Thin Film Electroluminescent Devices
R. Stevens, I. P. McClean, and M. R. Craven

Rapid Thermal Annealing of High-Melting-Point Films on Low-Melting-Point Substrates
S. E. Rosenberg, P. Y. Wong, and I. N. Miaoulis

A Production Planning Methodology for Semiconductor Manufacturing Based on Iterative Simulation and Linear Programming Calculations
Y.-F. Hung and R. C. Leachman


CORRESPONDENCE

Modeling of Integrated Circuit Yield Loss Mechanisms
Z. Stamenkovic, N. Stojadinovic, and S. Dimitrijev

Empirical Results on the Relationship Between Die Yield and Cycle Time in Semiconductor Wafer Fabrication
S. P. Cunningham and J. G. Shanthikumar

Wafer Level Sort Programming---Impact on EPROM Memory Retention
T.-S. Yeoh and S.-J. Hu

A Versatile Structure for On-Chip Extraction of Resistance Matching Properties
F. Larsen, M. Ismail, and C. Abel

Testing the Robustness of Two-Boundary Control Policies in Semiconductor Manufacturing
H. Yan, S. Lou, S. Sethi, A. Gardel, and P. Deosthali

Reduction of Loading Effect by Tungsten Etchback in a Magnetically Enhanced Reactive Ion Etcher
J. H. Ha, S. W. Kim, Y. S. Seol, H. K. Park, and S. H. Choi


Return to CPMT Transactions' Tables of Contents