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IEEE Transactions on
Semiconductor Manufacturing

August 1996, Volume 09, Issue 03

BEST PAPER AWARD

G. Cheek

PAPERS

Evolving Complexity and Cost Dynamics in the Semiconductor Industry

D. A. Hicks

Modeling the Growth of PECVD Silicon Nitride Films for Solar Cell Applications Using Neural Networks

S. S. Han, L. Cai, G. S. May, and A. Rohatgi

Sources and Transport Mechanisms of Gaseous Impurities in Vertical Thermal Reactors

N. K. Verma, C. Ma, E. Shero, and F. Shadman

Simple Performance Models for Integrated Processing Tools

S. C. Wood

Measurement and Control of a Residual Oxide Layer on ${\hbox{TiSi}}_2$ Films Employed in Ohmic Contact Structures

Z. Yu, P. Nikkel, S. Hathcock, Z. Lu, D. M. Shaw, M. E. Anderson, and G. J. Collins

Development of a TiW Plasma Etch Process Using a Mixture Experiment and Response Surface Optimization

D. A. Shumate and D. C. Montgomery

Small Signal Analysis of Source Vapor Control Requirements for APCVD

B. Mayer

Advanced Process Control of a CVD Tungsten Reactor

J. A. Stefani, S. Poarch, S. Saxena, and P. K. Mozumder

Single-Wafer Cluster Tool Performance: An Analysis of the Effects of Redundant Chambers and Revisitation Sequences on Throughput

T. L. Perkinson, R. S. Gyurcsik, and P. K. McLarty

Methods for Job Configuration in Semiconductor Manufacturing

D. P. Connors and D. D. Yao

A Queueing Network Model for Semiconductor Manufacturing

D. P. Connors, G. E. Feigin, and D. D. Yao

Diagnostic and Monitoring Tools of Large Scale Si-Manufacturing: Trace-Analytical Tools and Techniques in Si-Wafer Manufacturing

L. Fabry, L. Köster, S. Pahlke, L. Kotz, and J. Hage

A Statistical Methodology as Applied to a 256 Mbit DRAM Pass Transistor Design

P. K. Mozumder and A. Chatterjee

A Unified Yield Model Incorporating Both Defect and Parametric Effects

C. N. Berglund

Bipolar Integrated Kelvin Test Structure for Contact Resistance Measurement of Self-Aligned Implantations

L. K. Nanver, E. J. G. Goudena, and J. Slabbekoorn

CORRESPONDENCE

A Nonparametric Approach to Estimate System Burn-in Time

W.-T. K. Chien and W. Kuo

A Model for Radial Yield Degradation as a Function of Chip Size

D. Teets

Improved EEPROM Tunnel- and Gate-Oxide Quality By Integration of a Low-Temperature Pre-Tunnel-Oxide RCA SC-1 Clean

J. F. Buller, B. Bandyopadhyay, S. Garg, and N. Patel