The Decade of Materials: Novel Materials for the Connected Digital World 🗓 🗺

— materials for electronic, RF, photonic applications for 5G, displays, life sciences …

(This meeting has been postponed to a future date; we’ll let you know)

Speaker: Dr. Waguih S. Ishak, Division VP and Chief Technologist, Corning R&D Corporation, and Adjunct Professor, Electrical Engineering, Stanford University

Meeting Date: being rescheduled
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only (no cost): 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 2004eps.eventbrite.com

Summary: We just started a decade where novel materials will be crucial to many of the technological mega trends we are experiencing, from 5G wireless to augmented/virtual reality, to autonomous vehicles, to personalized medicine, and ML/AI. The talk will focus on materials from technology groups within Corning for electronic, RF and photonic applications in communications, displays, storage and life sciences.

Bio: Waguih Ishak received a B.S. (honor) in electrical engineering from Cairo University in 1971 and a B.S. (honor) in mathematics from Ain Shams University, Egypt, in 1973. He obtained his M.S. and Ph.D., both in electrical engineering, from McMaster University, Ontario, Canada, in 1975 and 1978, respectively. He also obtained the Stanford University Executive Program in 1999 and was awarded a D.Sc. Degree Honoris Causa from McMaster University in 2018.
From 1978 to 1987, he was a Member of Technical Staff at HP Labs. From 1987 to 2003, he was the Director of the Communications & Optics Research Laboratory at HP Labs, working on photonics and integrated electronics. From 2003 to 2005, he was the VP and Director of the Photonics & Electronics Research Lab at Agilent Labs responsible for R&D programs in photonics, high-speed electronics, sensors, semiconductor tests, wireless communications and optical consumer electronics. From 2005 to 2007, he was the CTO and Vice President of Avago Technologies (Now Broadcom).
From 2007 to 2016, Ishak was a Division VP and Director of the Corning West Technology Center in Palo Alto, California. In May 2016, he was appointed Division VP and Chief Technologist, responsible for strategic connections to Silicon Valley hotspots, VCs, startups and academia. In 2019, Ishak had an additional responsibility as an adjunct professor of electrical engineering at Stanford University.
Dr. Ishak’s teams’ contributions include the design and development of more than 40 lightwave test instruments, pioneering parallel optical transceivers up to 120 Gb/s, the optical and laser mouse inventions and development (more than a billion sold), numerous WDM components and subsystems, high-speed active optical cables, and novel display systems.
Dr. Ishak has authored more than 120 journal and conference papers, and four chapters in the “Handbook of Electronic Instruments.” He was named an inventor on seven U.S. patents. He is on the Technical Advisory Boards of UCSD, Santa Clara University, and McMaster University. He is a member of the VCAT of NIST and was a member of the National Academics Committee on “Harnessing the Light” resulting in the White House announcement of the Integrated Photonics Manufacturing Institute on October 2014 http://spie.org/x110433.xml.
Dr. Ishak is a Life Fellow of the IEEE. Ishak received the University of California Exemplary Service Award in 2015. Dr. Ishak’s current research interests include: optical and wireless communications, high-speed electronics, displays and material informatics (machine learning to uncover new materials.)

Heterogeneous Integration Roadmap: 3rd Annual Meeting 🗓 🗺

— future of mobile, HPC, automotive, 5G, health, Chiplets, work on 2020 Roadmap …

register
Dates: Thursday, February 20, 2020 (8:30 AM – 6:00 PM) and Friday, February 21, 2020 (8:30 AM – 4:00 PM)
Cost: $70 General Admission; $60 IEEE/ASME members and employees of SEMI member companies; $35 for retired, unemployed; free for full-time students. includes 2 lunches, wine-tasting
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas CA USA
Information and Reservations: 2002symp-eps.eventbrite.com

NOTE: No photographs or videos are allowed during the Symposium. (This announcement complies with IEEE policies.)
Program Outline: (details below)
Day 1: From the 2019 Roadmap to HIR 2020
— Plenary Speakers from Intel and Google, with views of the future
— Moderated Sessions on the Released Roadmap and what comes next
— California Wine tasting
Day 2: TWG Working Group Workshop for HIR 2020
— Special Forum on the Rise of Chiplets
— Working Group breakout Sessions for HIR 2020
— Cross-Working Group Collaboration meetings

Roadmap Sponsors:

Summary: We are entering the era of the digital economy and ubiquitous connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into our global society, and the plateauing of CMOS’s scaling advantage, continued progress now requires a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
The Heterogeneous Integration Roadmap (HIR) published in 2019 is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). This is a pre-competitive technology roadmap addressing this future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and our professional careers.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have released this new Roadmap — a broad and inclusive worldview that comprehends this diversity, developed by a group of leading technical experts. It was made available in 2019 for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, Feb 20, 2020: Implementation of HIR v1.0; Work on v2.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00 – 9:10: Start of Program; Welcome by Ajit Manocha, SEMI CEO, and Nicky Lu, Etron Chairman
9:10: HIR Symposium Objective
9:25 – 9:55: Plenary Speaker: Virtuous Cycle of AI, Dr Pradeep Dubey, Intel Senior Fellow & Director, Intel Parallel Computing Lab
10:05 – 11:05: Session 1 – Heterogeneous Integration for Communications, Chair: Amr Helmy, Univ of Toronto & IEEE Photonics Society
— 5G, RF and Analog Mixed Signal: Tim Lee (Boeing), Herbert Bennett (Alta Tech)
— Mobile: William Chen (ASE), Benson Chan (Binghamton University)
— Aerospace & Defense: Tim Lee (Boeing), Jeff Demmin (Keysight)
— WLP (Fan-in & Fan-Out): Rozalia Beica (iNEMI), John Hunt (ASE)
— Simulation: Chris Bailey (University of Greenwich), Xuejun Fan (Lamar University)
— Materials & Emerging Research Materials: Bill Bottoms (3MTS)
11:05 – 11:15: Q&A
BREAK
11:30 – 12:20: Session 2 – Heterogeneous Integration for Consumer & Industrial Applications, Chair: Ravi Mahajan, ASME EPPD & Intel
— Medical, Health & Wearables: Mark Poliks (Binghamton U), Nancy Stoffel (GE)
— SiP & Module: Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon), Erik Jung (IZM)
— Single Chip and Multi Chip Integration: William Chen (ASE), Annette Teng (Promex)
— Emerging Research Devices: Meyya Meyyappan (NASA Ames)
— Co-Design: Jose Schutt-Aine (University of Illinois)
12:20 – 12:30: Q&A
12:30 – 12:35: Thanks to Organizers and Patrons
12:35 – 1:30: LUNCH   (box lunch) and discussion time
1:30 – 2:00: Plenary Speaker: Dr. Hong Liu, The Role of Optics in Compute Infrastructure, Distinguished Engineer & Senior Director, Google Technical Infrastructure
2:00 – 2:50: Session 3 – Heterogeneous Integration for High-Performance Computing, Chair: Bill Bottoms, IEEE EPS & 3MTS
— High Performance Computing & Data Centers: Kanad Ghose (Binghamton University), Dale Becker (IBM), Rockwell Hsu (Cisco)
— 2D-3D & Interconnect: Ravi Mahajan (Intel), Subramanian Iyer (UCLA)
— Thermal Management: Madhusudan Iyenger (Google), Azmat Malik (Acuventures)
— Integrated Photonics: Amr Helmy (University of Toronto), Bill Bottoms (3MTS)
— Test: David Armstrong (Adventest)
2:50 – 3:00: Q&A
BREAK
3:15 – 4:15: Session 4 – Heterogeneous Integration for Special Applications, Chair: Tom Salmon, SEMI
— Automotive: Urmi Ray (iNEMI), Rich Rice (ASE)
— MEMS & Sensor Integration: Shafi Saiyed (ADI)
— Integrated Power Packaging: Patrick McCluskey (U-Md), Doug Hopkins (NCSU)
— Cyber Security: Sohrab Aftabjahani (Intel)
— Supply Chain: Paul Trio (SEMI)
— IoT: Robert Lo (ITRI)
4:15 – 4:25: Q&A
4:25 – 5:20: HIR Open Forum: Feedback & Comments
5:20 – 5:35: Next-Day TWG Workshop Preparation
Symposium Closing
5:45 – 6:45: California Wine Tasting

Friday, Feb 21, 2020: HIR Technical Working Group Workshop
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30 – 9:00: Registration and coffee at SEMI Hdqtrs, Milpitas
9:00 – 9:20: All-HIR TWG Overview; HIR 2020 Revision Preparation
9:20 – 10:00: “The Rise of Chiplets” Special Forum
— Invited Speakers: David Kehlet (Intel), Babi Vinnakota (ODSA)
10:00 – 11:30: TWG Breakout Workshop I
11:30 – 12:00: All-TWG Breakout Session Report
12:00: Lunch (box lunches provided)
1:00 – 1:30: Planning for ECTC HIR Workshop & 2020 HIR Events
1:30 – 3:00: TWG Breakout Workshop II
3:00 – 3:30: All-TWG Breakout Session Report
3:30 – 4:00: Closing Remarks and Wrap-Up
4:00 – 5:30: Space available for TWG informal discussions and Cross-TWG collaborations (optional)

Hosted by SEMI   SEMI 
(The first day had been planned for Samsung Foundry; however, due to an abundance of caution relating to staff and visitor health, Samsung has decided to limit large events on their San Jose campus. Our thanks to Samsung for their willingness to host.)
Health Alerts:
— please do not attend if you have been in China (excludes Taiwan) in the last 15 days. We will refund.
— please do not attend if you are not feeling well. We will refund.
— We are expecting a full house and are taking precautions to keep us all healthy. Avoid handshakes (try a fist-bump or short bow). Hand sanitizers will be provided. Microphones will be sterilized.

We thank our Annual Meeting supporters for 2020:
        GOOGLE     Cisco Silitronics


Recent Advances and Outlook for Heterogeneous Integration 🗓 🗺

— integrating dissimilar chips, 2.5 and 3D, various substrates, new processes, time-to-market, cost …

Speaker: John H. Lau, Unimicron Technology Corporation
register
Meeting Date: Friday, February 28, 2020
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members
Presentation Slides: “Recent Advances and Outlook for Heterogeneous Integration” (3.6 MB PDF)

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 2002eps.eventbrite.com
Summary: Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stacked) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. In the coming years we will see more implementations of higher levels of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the definition, classifications, applications, and trends in heterogeneous integration will be presented. Outline:
— Definition of Heterogeneous Integration
— Classifications of Heterogeneous Integration: on Organic Substrates; on Silicon Substrates (TSV-Interposers); on Silicon Substrates (TSV-less Interposers); on Fan-Out RDL Substrates; on Ceramics Substrates
— Applications of Heterogeneous Integration: of PoP; of CIS and Logic Chips; of LED and TSV-Interposers; of MEMS and Logic Chips; of VCSEL and PD
–Trends in Heterogeneous Integration


Bio: John Lau has more than 39 years of R&D and manufacturing experience in semiconductor packaging, and has published more than 490 peer-reviewed papers, has 30 issued and pending US patents, and 20 textbooks on, e.g., Heterogeneous Integration (Springer 2019). John has been an IEEE Fellow since 1994, and is an IMAPS and ASME Fellow.

IoT and PoE: An Overview, Applications and Future Directions 🗓 🗺

— sensors, hardware, data centers, App connections, new services, increased power, heat density …

Speaker: Baris Dogruoz, Ph.D., Cisco Systems, Inc.
register
Meeting Date: Thursday, November 21, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1911eps.eventbrite.com
Summary: IoT (the Internet of Things) entities make connection to applications, which enhance efficiency and create new and unique services. In order to support these connections, IoT-related hardware equipment ranging from sensors to data centers need to be designed accordingly and carefully. PoE (Power over Ethernet) reduces the volume of power cords, leading to a lower cost and less complicated infrastructure for data centers, facilities and smart structures — nevertheless with the penalty of increased power and heat density. This talk will give an overview of IoT and PoE markets, application examples with a hardware focus, and future directions in these areas.


Bio: Dr. Baris Dogruoz is at Cisco Systems. He has 15+ years of experience in thermal/fluids engineering and science, product development, technical consulting. His areas of interest: CFD/CHT and experimental methods in turbulent flow and heat transfer, thermal management of electronics, micro/meso/milli scale heat transfer, PCB modeling, renewable energy, data centers, Internet of Things (IoT), innovation, technology management.

System in Package (SiP) for Miniaturized Electronics Modules: An Update 🗓 🗺

— miniaturized modules, technology landscape, requirements, solutions, flexible electronics …

Speaker: Dr. Dongkai Shangguan, Vice President – Technology, Design & Engineering, Flex
register
Meeting Date: Wednesday, October 2, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1910beps.eventbrite.com
Summary: This presentation will review the SiP technology landscape, and discuss various solutions and competency requirements, for miniaturized modules for system integration across market segments. Reliability considerations for miniaturized devices and materials requirements for high-frequency applications will be discussed. Development of flexible electronics modules will be discussed as well.


Bio: Dr. Dongkai Shangguan is currently Vice President for Advanced Manufacturing Engineering at Flex. Previously, he served as the Chief Marketing Officer of STATS ChipPAC. Early in his career, Dr. Shangguan spent 10 years with Ford Motor Co. and Visteon Corporation where he held various technical and management responsibilities, and then 11 years at Flextronics where he was Vice President of Advanced Technology and Engineering Leadership.
Dr. Shangguan is an IEEE Fellow and has served on the iNEMI Board of Directors, the IEEE CPMT Society Board of Governors, and the IPC Board of Directors. He has received a number of recognitions for his contributions to the electronics industry, including the Outstanding Sustained Technical Contribution Award from IEEE CPMT, the William D. Ashman Achievement Award from IMAPS, Presidents Award from IPC, and Total Excellence in Electronics Manufacturing Award from the Society of Manufacturing Engineers.
Dr. Shangguan received his Bachelor of Science degree in Mechanical Engineering from Tsinghua University, China; MBA degree from San Jose State University; and Ph.D. in Materials from the University of Oxford, U.K. He conducted post-doctoral teaching and research at the University of Cambridge and The University of Alabama. Dr. Shangguan has published two books, authored/co-authored 250 technical papers and articles, and has been issued over 20 patents.

Trends and Opportunities in Silicon Photonics Packaging for Networking Applications 🗓 🗺

— SiPh packaging, large-scale data centers, interconnects, long-haul networking, Roadmap, integration …

Co-sponsored by the SCV Photonics Chapter
Speaker: Jie Xue, VP, Cisco
register
Meeting Date: Thursday, December 19, 2019 (was Friday, October 25: postponed)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1910eps.eventbrite.com
Summary: This talk will cover the new industry roadmap for high speed optics for large scale datacenters, interconnects, and long-haul networking applications using Silicon Photonics technologies, as well as discuss challenges/opportunities in SiPh packaging to enable this roadmap and pave the path for eventual integration of Switching ASICs that include Optics (aka: In-Package Optics).


Bio: Jie Xue leads Cisco’s Technology and Quality organization, a global team responsible for anticipating, developing, and providing technology innovations in support of Cisco’s supply chain. The team drives a competitive advantage by ensuring innovation and excellence in manufacturing technology, test and component engineering, advanced technology development, closed-loop quality management, and product compliance. These range from 100G heterogeneous silicon photonics to high-speed connectors and 2.5D/3D technologies, advanced PCBs, thermal cooling solutions, and advanced algorithms for automated decision-making.

Jie is an Institute of Electrical and Electronics Engineers (IEEE) Fellow, an International Microelectronics Assembly and Packaging Society (IMAPS) Fellow, an IEEE-Electronics Packaging Society (EPS) Distinguished Lecturer and served as President of EPS from 2014 to 2015. As President of EPS, she spearheaded the rebranding and revitalization of the Society to keep pace with the evolving microelectronics industry. She is a published author of more than 90 technical papers, hold 12 patents, and has served as a keynote speaker for domestic and international conferences.

Advanced Packaging Trends & Electronic Materials in Era of Digital Transformation 🗓 🗺

— integration technologies, new applications, trends in 5G, Artificial Intelligence, IoT, autonomous driving …

Speaker: Rozalia Beica, ­ Global Director Strategic Marketing, Electronics & Imaging Division, DuPont
register
Meeting Date: Friday, June 28, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1906eps.eventbrite.com
Summary: Digital transformation is further expanding into new markets bringing new application opportunities and driving increased adoption of electronics and semiconductor devices. The explosion of new applications is driving the semiconductor industry to transition from a technology node to an application driven industry. While advancing the technology node continues, new architectures and integration technologies are being developed to address increasing market requirements and the need of integrating more functionalities within smaller and more compact systems. A wide range of packaging technologies have already been successfully developed and adopted in the industry enabling single and multi-die packaging. While these technologies will continue to grow and further evolve, heterogeneous integration is gaining a lot of interest in the industry due to several benefits it can bring. This will also drive the need for more performing electronic materials and processes.
The presentation will provide an overview of the major trends (5G, Artificial Intelligence, IoT, Autonomous Driving, etc.) driving the semiconductor and packaging industry. The talk will highlight the various packaging platforms and their evolution as well as the material and processing challenges and needs driven by these applications.


Bio: Rozalia Beica is Global Director Strategic Marketing, DuPont, Electronics & Imaging Division. In her current role, Rozalia leads strategic marketing activities across Electronics & Imaging Division. She has 27 years of international working experience across various industries, including industrial, electronics and semiconductors. For 20 years she was involved in the research, applications and strategic marketing of Advanced Packaging technologies, with global leading responsibilities at specialty chemicals (Rohm and Haas Electronic Materials), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining DuPont, Rozalia was the CTO of Yole Développement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing.
Throughout her career, Rozalia has been actively supporting industry activities worldwide: Program Director of EMC3D Consortia, General Chair of IMAPS Device Packaging and Global Semiconductor and Electronics Forums, Technical Advisory Board Member at SRC, Member of the Executive Committee of ECTC, IMAPS SiP, ISQED, ESTC and member of several committees worldwide (ITRS, IWLPC, EPTC and EPS). Current industry involvements include: IMAPS VP of Technology, Technical Chair IMAPS Advanced SiP USA and SiP China Symposium, ECTC Assistant Program Chair, HIR WLP Chair, Advisory Board Member of 3DinCites and IMPACT Taiwan. She has over 150 presentations and publications (including 3 book chapters on 3D IC technologies), several keynotes, invited presentations and panel participations.
Rozalia has a M.Sc. in Chemical Engineering from Polytechnic University “Traian Vuia” (Romania), a M.Sc. in Management of Technology from KW University (USA), and a Global Executive MBA from Instituto de Empresa Business School (Spain).

3D X-ray Characterization; High Density Hybrid Bonding for 2.5D/3D Applications 🗓 🗺

— chip-stacking, microbumps, issues, new process, low cost, sensors, MEMS, computing …

12:00 – 12:30: “Non-Destructive Characterization of Advanced IC Packages with Buried Features using 3D X-ray”
Speaker #1: Thom Gregorich, Carl Zeiss PCS Inc.
12:30 – 1:15: “High Density D2W DBI Hybrid Bonding for 2.5D/3D Applications”
Speaker #2: Dr. Sitaram Arkalgud, Xperi
register
Meeting Date: Wednesday, April 10, 2019
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM First Presentation; 12:30 PM Second Presentation
Presentations-only: 12:00 noon (come at 11:45 or 12:15)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Co-sponsor: MEPTEC
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1904eps.eventbrite.com

First Talk Summary (Thomas Gregorich): For more than 40 years the semiconductor industry has been driven by silicon scaling: minimum CMOS feature size scaled from tens of microns down to a few nanometers. During the same period, minimum package feature size scaled much less, largely because it was more beneficial to scale the silicon than to scale the package. However, silicon scaling is slowing down and there are other challenges such as memory bandwidth and reliability which cannot be solved by silicon scaling. It is clear that package technology is being pushed out of its “comfort zone” and has entered an era of aggressive feature scaling and performance enhancement.
This presentation will explore the history of feature size scaling in wafer fabrication and the types of inspection and metrology systems which were developed to enable this scaling. Inspection and metrology process flows in wafer fabrication will be compared to inspection and metrology process flows in package assembly, and opportunities will be identified to enhance inspection and metrology systems in package assembly. The ZEISS Xradia Versa 620 X-ray Microscope and Measurement System will be introduced as a non-destructive solution to enhance package inspection and metrology during development and characterization, and several use cases will be presented.

Bio: Mr. Thomas Gregorich is Director of Business Development at ZEISS Semiconductor Manufacturing Technology where he is responsible for imaging products which support Advanced Packaging. Previously Mr. Gregorich held senior-level positions at Western Digital, Micron, Broadcom, MediaTek and Qualcomm. At Micron Mr. Gregorich qualified the Company’s first commercial TSV product. While at Qualcomm he established the Package Engineering department and for 12 years led the development of Qualcomm’s small form-factor package portfolio including NSP, CSP, BCC, QFN, POP and PIP. Prior to his position at Qualcomm, Mr. Gregorich worked for Motorola and had assignments in the Semiconductor Products Sector and Corporate Research, both in the United States as well as Japan, Taiwan and China. Mr. Gregorich has a BS in Mechanical Engineering from Bradley University, an MBA from Northern Illinois University and is a Senior Member of IEEE.

Second Talk Summary (Sitaram Arkalgud): Chip and wafer stacking have made major inroads into several semiconductor segments, including CMOS Image Sensors, MEMS and HPC. As stacking becomes a necessity, it continues to expand into DRAM, RF and other markets. Microbumps are today’s interconnect of choice, but they face issues of scalability and reliability, together with underfill and polyimide layers introducing thermo-mechanical issues which worsen with large dies. This talk describes a room-temperature hybrid bonding process that eliminates microbumps and associated organic layers, resulting in high reliability, low cost, and high density interconnects with improved thermo-mechanical performance. It will present our D2W DBI development work targeting 2.5D and 3D applications.

Bio: Sitaram Arkalgud is driving the application of Xperi bonding technologies (ZiBond® and DBI®) in numerous 3D products across the industry. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Xperi (Invensas), he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, Cu/Cu wafer/die bonding and wafer thinning for 3D ICs. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 45 U.S. patents. Sitaram holds Masters and Ph.D. degrees in Materials Engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a Bachelor’s degree in Metallurgical Engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.

Designing Plastic Parts for Multi-Jet Fusion vs Injection Molding + Tour 🗓 🗺

— tour, comparison, considerations, cost, schedule, quality, case study, HP Z3D camera …

Speaker: John Briden, Application Development Consultant, HP 3D Printing Group
register
Meeting Date: Thursday, March 14, 2019
Time: Registration/snacks 6:00 PM; Lab Tour 6:30 PM; Presentation 7:00 PM
Cost: $10 general admission; $0 IEEE members (use IEEE member number)
Sponsor: ASME SF Bay Area Section
Location: H-P, 1501 Page Mill Road, Palo Alto
Reservations: www.eventbrite.com/o/asme-santa-clara-valley-section-484885605 (required; no walk-in’s)
Summary: This presentation will cover how the two technologies — Multi Jet Fusion (MJF) and Injection molding (IM) — work, with a more detailed explanation of MJF. The speaker will discuss the reasons for considering the use of MJF instead of IM based on a product development framework of cost, schedule, quality and unique value. He will use that framework for a more detailed comparison of the technologies. The presentation will highlight a specific case study that the speaker had direct personal experience with — the development of the HP Z3D Camera. There will be some sample parts of MJF to pass around.

Bio: John Briden is a Stanford Mechanical Engineering graduate who has spent a career developing products at leading consumer electronics companies like Apple and HP Inc. About a year and a half ago he joined HP’s Multi-Jet-Fusion 3D printing group to help usher in the next industrial revolution with 3D printing for production.

TI Coordinates:
TI Conference Center, Santa Clara
37.375686
-121.999004
SEMI coordinates:
SEMI World Hdqtrs, Milpitas
Lat: 37.427
Long: -121.8958

Sponsors Needed for STEM Internships for this Summer 🗓

— highschool tech students, funding, companies needed, summer workers, career development …

Your EPS chapter has voted to lend support to the Cupertino and Sunnyvale Rotary Clubs, which are working with the Fremont Union High School District to kick off a paid high school summer internship program for a select group of students at Fremont High School in Sunnyvale. The goal of the pilot is to increase interest in STEM careers by providing students with the opportunity to work side-by-side with engineers or technicians in a company and apply what they’ve learned from the Engineering Design Pathway course(s) they’ve completed. Rotary is looking for companies to either:

1. Provide paid internship opportunities (up to 10 internships). We have funding to cover 50% of the wage cost ($15/hour)for a 6-week, 20-hour per week internship. Companies would provide funding to cover the remaining 50% ($900 per internship for a 20-hour per week internship; or $1800 per internship if sufficient funding is obtained for 40-hour per week internship);

2. Provide financial support as a Program Sponsor (We need to raise $9000 to be able to offer students a 6-week, 40-hour per week, internship).

Note that Fremont Union High School District will have a 3rd Party who will take on the “Employer of Record” role, to handle the payroll services as well as the insurance to cover the students.

If your company is interested in participating in this initiative, please have them contact: Steve Onishi (Co-Chair, Workforce Development Committee, Cupertino Rotary) at steve.onishi@gmail.com or 408.621.4353.