2D to 3D Package Architectures: Back to the Future 🗓 🗺

— scaling, heterogeneous integration, impact on power, performance, latency, nomenclature for package architectures, current metrics, projections …

Speaker: Dr. Raja Swaminathan, Package Architect
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Meeting Date: Thursday, May 3, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: (URL) 1805aeps.eventbrite.com
Summary: Moore’s Law Scaling has driven electronics industry growth and new package architectures (including 3D architectures and architectures currently defined as 2.1D, 2.3D or 2.5D architectures) are projected to be major enablers to maintain the pace of Moore’s law scaling and enable heterogeneous integration. Historically, packaging has scaled sufficiently to act as a space and electrical transformer to enable transistor/silicon scaling, and innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. With an increasing drive for heterogeneous integration, packaging is being increasingly challenged to deliver power-efficient, high bandwidth on/off package low power links and meet diverse functionality ranging from high performance servers to flexible, wearable electronics. This talk will introduce a new IEEE standardized industry nomenclature on package architectures covering and clearly demarcating both 2D and 3D constructions, as well as highlight the key metrics driving the evolution of these architectures, their current values (based on the state of the art) and projections for the next 5-10 years. This is expected to drive focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next generation requirements in the 2D-3D architecture space.

Bio: Dr. Raja Swaminathan is an IEEE senior member and was a package architect at Intel for next generation server, client and mobile products. His expertise is on delivering integrated HVM-friendly package architectures with optimized electrical, mechanical, and thermal solutions. He is an IEEE, ITRS and iNEMI Roadmap author on packaging and design, and recently drove industry convergence of 2D and 3D architecture nomenclatures and design, process and electrical metrics. He has also served on IEEE micro-electronics and magnetics technical committees and has been key note speaker in electronics conferences. He has 26 patents and 25 peer-reviewed publications and holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University.

Reliability for the 21st Century: Meeting Challenges of New Packaging Technologies and New Markets 🗓 🗺

— complexity, feature sizes, physics of failure, damage metrics, packaging design, qualification, proposed methodologies …

Speaker: Dr. Milena Vujosevic, TDK-InvenSense
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Meeting Date: Wednesday, April 25, 2018
Sponsors: EPS Chapter; Reliability Chapter; MEMS & Sensors Chapter
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1804eps.eventbrite.com

Summary: Electronics components are constantly evolving, with new types of devices rapidly entering new markets. New technologies are significantly more complex than the technologies of the past, characterized by smaller features and heterogeneous integration. New markets, on the other hand, bring about new types of environments, new customer expectations and new usage models. Existing industry standards often do not provide sufficient guidance for qualification of new technologies. This requires packaging design and reliability practitioners to look beyond the existing reliability standards so that they make sure their components are designed correctly for the new field.
This talk discusses challenges with many standards-based approaches for definition of qualification requirements and proposes a methodology for overcoming those challenges. The proposed methodology leverages advanced tools of contemporary engineering to comprehend use conditions and failure physics. The special focus is on the essential role of the physics-based damage metrics in translating from use condition to test conditions and in design for reliability. Examples from the area of electronic packaging design and qualification published in the literature will be used to discuss the proposed methodology relative to the standards-based qualifications.


Bio: Dr. Milena Vujosevic is a senior technologist and manager with more then 20 years of experience in the semiconductor industry working in the areas of technology development, design, and reliability. She is a Senior Director for Advanced Packaging at TDK-InvenSense, which she joined early in 2018. She is responsible for MEMS sensors packaging technology and manufacturing covering multiple technologies: motion, pressure, ultrasonic sensors for mobile, automotive and drone applications. Before that she spent 13 years at Intel as a Principal Engineer and Sr. Manager working in Intel’s packaging and reliability organizations focusing on  pathfinding and development of advanced IC packaging. Prior to joining Intel she worked for Motorola in the area of MEMS sensors for automotive, medical and consumer electronics markets. Milena has published more then 60 papers, 3 book chapters and delivered multiple invited talks. She is a recipient of the 2011 ASME Woman Engineer of the Year award for significant achievements in the field of electronic and photonic packaging. Milena has a PhD in Mechanical Engineering.

Towards Energy Sustainability in Data Centers: Some Thoughts on Energy, Entropy, and Water 🗓 🗺

— powering the internet and cloud, cooling, energy use, data center design, non-traditional approaches …

Speaker: Dr. Alfonso Ortega, Dean of the School of Engineering, University of Santa Clara
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Meeting Date: Wednesday, May 9, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1805eps.eventbrite.com

Summary: The fabric that connects billions of people (through mobile and wearable devices), things (Internet of Things) and services (Internet of Services) is composed of (1) the digital engines or factories that store and process data (Data Centers, the “cloud”) and (2) the wired and wireless network that transmits that data (the Internet). It is easy to overlook the silent third partner in this alliance of technologies which is (3) the energy infrastructure required to power both the digital engines and the network.
In this talk I will discuss the thermodynamics of data centers starting with the environmentally horrifying observation that almost all of the electrical power consumed by the “electronic engines” or servers in data centers is dissipated as heat. In efforts to save energy in the cooling of data centers, the hyperscale industry has adopted the use of outside air for cooling, coupled with evaporative air conditioning using water. In this context, swapping the consumption of one resource (electrical power required for mechanical cooling) with another (water for evaporative cooling) leads to confusion because they cannot necessarily be compared using energy units or metrics. Without offering solutions, in this talk I will focus on possible ways to think about the issue using well known but non-traditional approaches that involve second law and sustainable engineering thinking.
The evolving notion that we are in the midst of a “Fourth Industrial Revolution” was described by Klaus Schwab, Founder and Executive Director of the World Economic Forum, in the following way: “The possibilities of billions of people connected by mobile devices, with unprecedented processing power, storage capacity, and access to knowledge, are unlimited. And these possibilities will be multiplied by emerging technology breakthroughs in fields such as artificial intelligence, robotics, the Internet of Things, autonomous vehicles, 3-D printing, nanotechnology, biotechnology, materials science, energy storage, and quantum computing.” We need to understand how to make this happen.


Bio: Dr. Alfonso Ortega received his B.S. from The University of Texas-El Paso, and his M.S. and Ph.D. from Stanford University, all in Mechanical Engineering. Dr. Ortega was on the faculty of the Department of Aerospace and Mechanical Engineering at The University of Arizona in Tucson for 18 years, where he directed the Experimental and Computational Heat Transfer Laboratory. From 2004 to 2006, Dr. Ortega was the Program Director for Thermal Transport and Thermal Processing in the Chemical and Transport Systems Division of The National Science Foundation in Arlington, Virginia, where he managed the NSF’s primary program funding heat transfer and thermal technology research in U.S. universities. Dr. Ortega is an internationally recognized researcher in the areas of thermal management of data centers and electronic systems, convective and conjugate heat transfer in complex flows, experimental measurements in the thermal sciences, and thermal management in energy systems.
He is the author of over 300 journal and symposia papers, book chapters, and monographs. Dr. Ortega is a Fellow of the ASME. He is the recipient of the National Science Foundation Presidential Young Investigator Award, the ASME Electronic Packaging Division Thermal Management Award, the SEMITHERM Significant Contributor Award, and the Harvey Rosten Award for Excellence. He has been a an Associate Editor of the ASME Journal of Heat Transfer, Associate Editor of the ASME Journal of Electronic Packaging and Guest Associate Editor of the IEEE Transactions on Components, Packaging, and Manufacturing Technology. He has chaired the ASME K16 Committee on Heat Transfer in Electronic Equipment, the ASME Electronic and Photonic Packaging Division, the IEEE ITHERM Symposium, the IEEE SEMITHERM Symposium, and the ASME InterPACK Conference.

Trends and Transitions in Semiconductor Packaging 🗓 🗺

— business models, supply chain, technology requirements, forecast for 2018 and 2019 …

Speaker: Dan Tracy, Senior Director Industry Research & Statistics, SEMI
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Presentation Slides: “Trends and Transitions in Semiconductor Packaging” (1 MB PDF)
Meeting Date: Wednesday, February 14, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1802eps.eventbrite.com
Summary: While on the heels of a strong growth year, there are a number of transitions and inflection points influencing the future of semiconductor packaging. Such trends include changes in business models, a changing supply chain, and packaging technology requirements that are affecting the materials market. This presentation will highlight these changes and transitions, and it will also include the SEMI forecast for packaging material for both 2018 and 2019.


Bio: Dr. Dan Tracy, Sr. Director of Industry Research and Statistics at SEMI, is responsible for developing and executing the global strategy for SEMI industry research and statistics products and services. Current market statistics products include monthly and quarterly data programs covering semiconductor capital equipment, materials and components, with in-depth annual reports on a variety of topics such as packaging materials and trends in the China market. Tracy is responsible for preparing market reports and presenting on trends impacting the electronic materials and equipment markets globally. In addition, Tracy is responsible for managing market statistics partnerships globally.
Prior to joining SEMI in 2000, Tracy was a Research Associate with Rose Associates, a prominent market research and consulting firm specializing in electronics materials. Prior to this, Tracy was employed at National Semiconductor’s Package Technology Group.
Tracy has a Ph.D. in materials engineering from Rensselaer Polytechnic Institute, a M.S in materials science & engineering from Rochester Institute of Technology and a B.S. in chemistry from State University of New York (SUNY) College of Environmental Science and Forestry.

Heterogeneous Integration Roadmap Committee Meeting 🗓

— disruptive change, pace of innovation, future requirements, emerging devices and applications …

Conveners: Prof. Subramanian (Subu) Iyer, UCLA; and Dr Meyya Meyyappan, Chief Scientist for Exploration Technology, Ames Research Center, NASA
Welcoming Speaker: Samar Saha, Electron Devices Society President
(no registration required)
Meeting Date: Sunday, December 3, 2017
Time: 6:00 – 7:30 PM
Cost:none (all are invited to attend)
Location: Hilton S.F. Union Square (Room: Union Square 13)
Reservations: not required
Summary: Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. While the pace of innovation is increasing to meet these challenges, the crucial question is what will be the critical paths going forward?
The Heterogeneous Integration Roadmap EDS President Samar Saha, a Plenary Lecture by Subu Iyer of UCLA, followed by a moderated discussion on what the HIR road map means to the device community, including a discussion on emerging devices and applications.

Heterogeneous Integration Roadmap Symposium 🗓 🗺

— end of CMOS scaling, difficult challenges, potential solutions, future vision, research, academia, labs, collaboration …

register
Date: Thursday, February 22, 2018
Time: 8:30 AM to 6:00 PM
Cost: $40 IEEE members. students, unemployed, $50 non-members ($10 more, after Feb. 9th)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1802symp-eps.eventbrite.com

Program Outline:
Download Full Program, Hotel Recommendations
— Presentations from HIR Technical Working Group chairs
— Overview from HIR International Roadmap Committee
Sponsors: 
       
We thank our financial supporters:
 
 
 



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.

We firmly believe that the Heterogeneous Integration Roadmap, founded with initiative from the three IEEE Societies — EPS, EDS & Photonics — and in collaboration with SEMI & ASME’s EPPD, has expanded to embrace innovations wherever they arise and promote collaboration wherever possible to accelerate progress in this disruptive digital landscape. Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity and assembled a group of leading technical experts to develop the Roadmap. The first work product of the Roadmap team will be presented by the chairs of the 20 Technical Working Groups for review and feedback.

Plenary Talk: “Synergistic Growth of AI and Silicon Age 4.0 through Heterogeneous Integration of Technologies” — Dr. Nicky Lu, Chairman, CEO & Founder, Etron Technology, Inc., and Managing Board Director, Taiwan Semiconductor Industry Association (TSIA)

Closing Remarks — Dr. Gaurang N. Choksi, Intel: Vice President, Technology and Manufacturing Group; Director, Assembly and Test Technology Development Core Competencies

Program Agenda
8:30: Registration and refreshments
9:00: Start of Program
Download Full Program, with topics, speakers
5:30 – 6:00 pm Wrap-Up

Roadmap Working Groups:
HI for Market Applications
• Mobile
• IoT
• Medical and Health & Wearables
• Automotive
• High Performance Computing and Data Center
• Aerospace and Defense
Heterogeneous Integration Components
• Single-Chip and Multi-Chip Packaging (including Substrates)
• Integrated Photonics
• Integrated Power Electronics
• MEMS & Sensor Integration
• RF and Analog Mixed-Signal Design
• Co-Design and Simulation – Tools & Practice
Cross Cutting topics
• Materials & Emerging Research Materials
• Emerging Research Devices
• Interconnect
• Test
• Supply Chain
• Security (Cyber)
Integration Processes
• SiP
• 3D +2.5D
• WLP (fan in and fan out)

Bio: As a researcher, design architect, entrepreneur and chief executive, Dr. Nicky Lu has dedicated his career to the worldwide IC design and semiconductor industry. He also co-founded several other high-tech companies including Ardentec, Global Unichip and GTBF Corporations. Dr. Lu worked for the IBM Research Division and then the Headquarters from 1982 to 1990 and won numerous IBM recognition awards, including an IBM Corporate Award. He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs over hundreds of billions dollars. Dr. Lu designed several High-Speed CMOS DRAM (HSDRAM) chips, with all top worlds’ records of performance. He was a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan semiconductor industry in early 1990s, also created many Taiwan companies as prominent silicon-chip suppliers. Since 1999 he has pioneered Known-Good-Die Memory Products enabling 3D stacked-dices system chips; this work summoned the new rise of an IC Heterogeneous Integration Era as described in his ISSCC-2004 plenary talk, demonstrating a new 3D-IC trend. He was a keynote speaker at the 2016 A-SSCC disclosing Silicon-Age-4.0 Era with a new Virtual Moore’s Law as a indicator of continual economic growth.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 30 U.S. patents and has published more than 60 technical papers. He serves as Managing Board Director and was Chairman of TSIA, as Board Member of Global Semiconductor Alliance (GSA) and GSA’s General Chair (2009 to 2011), and Chairman of WSC (World Semiconductor Council) from 2014 to 2015. He received the Scientific Management Award (2012) from Chinese Society for Management of Technology and Taiwan’s Golden Merchant Award (2007) from General Chamber of Commerce. He is an Outstanding Alumnus of National Taiwan University, a Chair Professor and an Outstanding Alumnus of National Chiao Tung University, an IEEE Fellow, the recipient of the IEEE 1998 Solid-States Circuits Award, a member of NAE (National Academy of Engineering of USA), and recipient of a SEMI Industry Contribution Award in 2017.


Bio: William (Bill) Chen currently holds the position of ASE Fellow and Senior Technical Advisor at ASE Group. Prior to joining ASE, he was the Director at the Institute of Materials Research & Engineering in Singapore. Bill retired from IBM Corporation after a career spanning over thirty years in various R&D and managerial positions. He has held adjunct and visiting faculty positions at Cornell University, Hong Kong University of Science and Technology, and Binghamton University. Bill is the chair of the newly formed Heterogeneous Integration Technology Roadmap for Semiconductors, an initiative addressing technologies for the IoT/IoE/cloud computing era, jointly sponsored by IEEE EPS, EDS, Photonics Societies, ASME’s EPPD, and SEMI. He also chairs SEMI’s Advanced Packaging Committee. In 2009, Bill received the InterPACK Excellence Award for his contributions, and in 2010, he was presented with the IEEE EPS Society David Feldman Outstanding Contribution Award. He is a past President of the IEEE EPS Society and he has been elected a Fellow of IEEE and a Fellow of ASME. Bill received his B. Sc. from London University, M.Sc. from Brown University and Ph.D. from Cornell University.


Bio: Dr. W. R. “Bill” Bottoms, the holder of a Ph.D. from Tulane University, has an extensive background in academia, venture funding, and in the commercial semiconductor equipment sector. Since founding 3MTS in 1999, Bill Bottoms has provided strategic leadership and vision in keeping with the promise of the 3MTS business model. Dr. Bottoms has also served on a number of important government and industry committees and advisory positions. Key posts include chairmanship of the subcommittee of the Technical Advisory Committee of the United States Commerce Department’s Export Control Commission for Semiconductor Equipment and Materials.
Shortly after receiving his doctorate in physics, Dr. Bottoms joined the electrical engineering faculty of Princeton University, where he remained until 1976. He then joined Varian Associates in Palo Alto, as manager of research and development, and he was later named president of Varian’s newly formed semiconductor equipment group. After leaving Varian, he was senior vice president and general partner at Patricof & Co. Ventures, Inc., an international venture capital firm. He founded Third Millennium Test Solutions in March 1999.

Heterogeneous Packaging Integration for Electronics Systems 🗓 🗺

— mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast …

Speaker: Dr. John H Lau, ASM Pacific Technology
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Presentation Slides: “Fan-Out Wafer-Level Packaging
for 3D IC Heterogeneous Integration”
(3.4 MB PDF)
Meeting Date: Thursday, January 25, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only (no cost): 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1801eps.eventbrite.com

Summary: Because of the drive of Moore’s law, compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. It has been a very “fancy” name in semiconductor packaging for the past few years. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem, rather than integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more implementations of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and lower gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

SoC: Apple’s application processor (A10 and A11)
SiP: Amkor’s SiP for automobiles; Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer): Leti’s SoW; ULCA’s SoW
Heterogeneous Integration with TSV-Interposers: TSMC/Xilinx’s CoWoS; AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer; Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer: Xilinx/SPIL’s TSV-less SLIT; SPIL/Xilinx’s TSV-less NTI; Amkor’s TSV-less SLIM; ASE’s TSV-less FOCoS; MediaTek’s TSV-less RDLs by FOWLP; Intel’s TSV-less EMIB; Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM; Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer; Cisco/eSilicon’s TSV-less Organic Interposer; ITRI’s TSV-less TSH; Shinko’s TSV-less i-THOP


Bio: John H. Lau has been a senior technical advisor of ASM since 2014, an ITRI Fellow of Industrial Technology Research Institute for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at HPLab/Agilent in California for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on flip chip technologies, WLCSP, BGA, TSV for 3D integration, advanced MEMS packaging, and reliability of 2D and 3D IC interconnections. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Mold Compound Interactions in Cu-Al Wirebonded ICs Operating in Harsh Environments 🗓 🗺

— high reliability, intermetallic growth, bond interface, formulations, temperature, bias, predictive model …

Speaker: Luu Nguyen, TI Fellow, Texas Instruments
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Meeting Date: Thursday, October 26, 2017 (changed from Sept. 13th)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1710cpmt.eventbrite.com
Summary: For high-reliability applications in harsh environments, better understanding of the acceleration factors under the stresses of operation is required. Prolonged exposure of copper wires at elevated temperatures can result in excessive intermetallic growth and degradation of the bond interface. Mold compounds used for encapsulation can vary widely in their formulations including ionic content, pH, porosity, and diffusion rates. Selection of the right material combination plays a key role in defining the lifetime of the wirebonded system. This talk will discuss the combined effect of various operational parameters such as temperature and bias, along with material properties, in the development of a model to predict the remaining useful life of Cu-wirebonded packages.


Bio: Dr. Luu Nguyen is a TI Fellow at Texas Instruments, working on printed electronics, wafer level packaging, high-voltage packaging, and design for manufacturability. He received his Ph.D. in Mechanical Engineering from MIT, and has worked at IBM Research and Philips Research. He coedited two books on packaging, and has over 200 publications. He has over 70 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He received two Best of Conference Awards, one Best Poster of Conference Award, and eight IMAPS and IEMT Best of Session Conference Awards. He received the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award. Other awards also include the 2003, 2014, 2015, and 2016 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer.

Comparison of Die Singulation Techniques 🗓 🗺

— die thinning, stealth laser, laser abrasion, plasma etch, rotary blade, results …

Speaker: Dr. Annette Teng, Chief Technology Officer, Promex Industries
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Presentation Slides: “Comparison of Singulation Techniques” (5 MB PDF)
Meeting Date: Thursday, September 28, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1709bcpmt.eventbrite.com
Summary: Wafer thinning and singulation is a critical process for successful miniaturization and high density packaging. A comparison of the latest die singulation techniques will be presented based on dicing yields and cost. These include stealth laser, laser abrasion, plasma etch and conventional rotary blade. Some results of stealth laser on singulated II-VI and III-V type dies will be presented in collaboration with Disco.


Bio: Annette Teng is currently the Chief Technology Officer at Promex Industries, which is a fast-turn subcontractor located in Silicon Valley. She has previously worked in components packaging and assembly at Philips Semiconductor, Linear Technology and Corwil Technology. Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years. She also worked at the Hong Kong University of Science and Technology to initiate their electronics packaging programs in 1997 to 2000. She has been active in IEEE-EPS (CPMT) activities locally and overseas. She is currently the Chair of the IEEE-EPS (CPMT) Santa Clara Valley/Bay Area Chapter.
She graduated with a Ph.D. in Materials Engineering from University of Virginia after receiving a BS from Sweet Briar College.

How to Peel Ultra-Thin Dies from Wafer Tape 🗓 🗺

— bending stress, die strength, peel force, die structures, wafer processing steps, TSVs, pickup methods, experimental verification …

Speaker: Dr. Stefan Behler, Senior Expert Process Engineer, Besi Switzerland AG
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Presentation Slides: “How To Peel Ultra Thin Dies From Wafer Tape” (1 MB PDF)
Meeting Date: Thursday, December 7, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1712cpmt.eventbrite.com
Summary: The four major key properties for successful, damage-free ultra-thin die (< 50 um thick) pickup from a wafer foil are described in detail: die bending stress, die strength, edge peel force, and bulk peel force. First, bending stress for different pickup methods (multi stage, multi disc, multi needle) are calculated and compared using a dynamic FEA model. Second, we summarize how the die strength is influenced by die structures and wafer processing steps, especially by thinning and dicing methods. In addition, we present die strength measurements for TSV test dies. Third, the property "wafer foil edge peel force" is introduced, and the dependency on the dicing method is experimentally verified. It clearly shows, that dicing-before-grinding is to be preferred over single cut dicing. Fourth, we give an overview of bulk peel forces of various commercial wafer foils. Values are taken from datasheet specifications, and compared using Kendall’s equation. Bio: Stefan Behler received his M. S. in experimental physics from the University of Göttingen (Gemany) in 1990, and his Ph.D. in physics from the University of Basel (Switzerland) in 1994. He was awarded an Alexander von Humboldt fellowship for a 2-year research project at the Lawrence Berkeley National Laboratory. The project was aimed at the investigation of surface chemistry of noble metals. In 1996 he joined the company Besi (formerly ESEC) focusing on process technology of die bonding. He is currently project manager for ultra-thin die applications at Besi Switzerland.