Enabling System Performance through Practical Thermal Innovation

Speaker: (name, affiliation)
Presentation Slides: “title” (xx MB PDF) after meeting
Meeting Date: (day), January xx, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1901eps.eventbrite.com
Summary: There are tremendous challenges of increasing total power as well as high localized heat flux resulting from the growing push for heterogeneous integration on silicon and at the package level.
These challenges dictate that a thermal solution needs to be architected based on these factors: current density; power mapping; package structure; and assembly and reliability requirements.
This talk will explore the impact of selected thermal solutions at the packaging and assembly levels, as well as at the system level. It will emphasize how to co-design the thermal architecture with performance, reliability, mechanical and assembly requirements. We focus on having a full understanding of the end-user application. Also, this talk will disclose an innovative thermal solution that can extend the cooling limit by up to 50%.

Bio: Dr. Gamal Refai-Ahmed is a technical director at Xilinx, in San Jose. He is an ASME Life Fellow, a Fellow of the Canadian Academy of Engineering, and a Distinguished Engineer (and Adjunct Professor) at SUNY Binghamton. He obtained the M. A. SC. and Ph. D. degrees in Mechanical Engineering from the University of Waterloo. Gamal has made important contributions to electronics packaging and development of electronics cooling technologies for the consumer electronics, telecommunications and energy industries. He is the author of more than 90 technical papers and more than 100 US patents/International Patents/Pending patents.
Gamal is an Associate Editor of the IEEE/EPS Transactions on Components, Packaging and Manufacturing Technology, and the ASME Journal of Thermal Sciences and Engineering and Applications. He is the recipient of the 2008 Dxcellent Thermal Management award, 2010 Best Associate Editor J Electronics Packaging, 2010 Calvin Lecture and 2013 K16-Clock award in recognition for his scientific contributions and leadership in promoting best electronics packaging engineering practices. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation, the 2015 ASME service award and the 2016 IEEC SUNY-Binghamton Innovation leader of the year.

Improving the IEEE: Issues, Ideas, Best Practices ๐Ÿ—“ ๐Ÿ—บ

— listening session, better methods/tools, local needs, actionable, with Division Director …

[Whether or not you can attend, you can leave suggestions for improvements in the COMMENTS box below.]
Speaker: Dr. Renuka Jindal, Director, IEEE Division I; and Eminent Scientist and CTO, Vanderziel Institute of Science and Technology, LLC.
Meeting Date: Saturday, December 1, 2018
Time: 2:00 – 4:00 PM
Cost: none
Sponsors: SCV chapters of the CAS, EPS, SSCS, EDS, ComSoc, Nano (plus other) Societies/Councils

Location: Santa Clara University (Benson 21), Santa Clara (free parking in the SCU garage) – Click for full-size map
Reservations: 1812eps.eventbrite.com (no charge)
Summary: This will be an event “for listening to” engineers and managers in Silicon Valley who have ideas for improving the IEEE, or have issues they’d like to raise. With input and grass-roots suggestions for improving the IEEE, I intend to provide actionable feedback at the IEEE TAB and BOD level. Your input will be critical in shaping the future of the IEEE and will need your active support to make this a reality.
If you wish to bring specific thoughts about IEEE changes, improvements and growth, be prepared to present them to the group for, say, 5 minutes, for discussion and enhancement. The meeting secretary will take notes, along with any handouts you provide, and ask for others who would like to be further involved with your specific suggestion. Renuka will receive your inputs and the summary, and is taking steps to allow him to gather world-wide input on these specific ideas that can inform and support the issues that are raised by our SV community of entrepreneurs.

Bio: Dr. Renuka Jindal’s technical focus has been on research and teaching in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications and biological systems. He was with Bell Labs at Murray Hill, Princeton and Whippany, NJ as a distinguished member of technical staff for 22 years, bridging both technical and administrative roles. Highlights include his pioneering work in developing a physical understanding of noise in MOS devices with few hundred nanometers regime channel lengths and ultra-low noise amplification of fiber-optic signals. Until recently, he has served as Professor of Electrical and Computer Engineering, University of Louisiana at Lafayette.
As a 41 year veteran of IEEE with a dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS president in 2010-2011, and now serves as Director of IEEE Division I, sitting on the IEEE Board. As EDS president he formulated the vision and mission of EDS, enhancing member benefits and launching a plethora of initiatives reversing the decline in EDS membership. He brought together 6 societies and 1 council to launch the highly successful IEEE Journal of Photovoltaics, mushrooming IEEE’s share in the PV space. He Launched the EDS webinar series serving the practicing engineer, now considered a best practice in IEEE. And he Launched the 1st EDS OPEN ACCESS Journal J-EDS. He is also a recipient of the IEEE 3rd Millennium medal.

Please summarize your suggested changes/improvements in the COMMENTS box below, or email them to the Webmaster.

FPGA Heterogeneous Packaging Applications: Trends and Challenges ๐Ÿ—“ ๐Ÿ—บ

— HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution …

Co-sponsored by the Solid State Circuits Chapter
Speaker: Suresh Ramalingam, PhD., Fellow, Manager Advanced Packaging Interconnect Technology Development, Xilinx
Meeting Date: Wednesday, November 14, 2018
Time: 11:30 AM Registration (and pizza/water); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1811eps.eventbrite.com

Summary: Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoSยฎ/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.

Bio: Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from the Massachusetts Institute of Technology. He holds 24 US Patents, the 2013 SEMI Award, the Ross Freeman Award for Technical Innovation, ECTC 2011’s Conference Best Paper Award, and IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D. He started his career at Intel developing Organic Flip Chip Technology for microprocessors which was implemented on Pentium I (Intel’s first flip chip product for laptops) in 1997. As one of the co-founders and Director of Packaging Materials at Scion Photonics, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D for Xilinx FPGA products.

The Road Ahead: Outlook for the Electronics Packaging Industry ๐Ÿ—“ ๐Ÿ—บ

— projections for AI, autonomous vehicles, crypto, OSATs, foundries, outlook …

Speaker: E. Jan Vardaman, President, TechSearch International, Inc.
Presentation Slides: “The Roadย Ahead: Outlook for the Industry” (2 MB PDF)
Meeting Date: Monday, October 22, 2018
Time: 12:30 PM Registration, lunch, and presentation (ending at 2:30 PM)
Cost: $25

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: fs24.formsite.com/meptec/form171
Summary: The semiconductor industry has seen record growth in the last few years, but with slowing growth in smartphone shipments and PC sales, what’s next? What will drive growth in advanced packaging? Is it Game Over for Cryptocurrency? Artificial Intelligence and automotive electronics are bright spots, but what types of packages will be used? How will OSATs benefit and what role will the foundry play? This presentation will examine economic and technology trends and provides an outlook for the industry.

Bio: Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia, and on the US mission to study manufacturing in China. She is a member of IEEE EPS, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE EPS Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industryโ€™s first pre-competitive research consortium.

10th Annual Soft Error Rate (SER) Workshop – Details

— Detailed descriptions of the talks at the SER Worshop (preliminary) …

Below are summaries of each of the tutorials and talks (not in the order in which they will be given). Return to this page following the Workshop to download PDFs of the slides and access links to the lecture video recordings.

Presenter Title Details
Eric Crabill, Xilinx Prerecorded Tutorial: Single Event Effects (Please view before attending; link will be sent) This tutorial is a technical backgrounder on Single Event Effects (SEE) in semiconductor devices, to establish a baseline understanding of origins, effects, mitigation, and testing. Key points made in this presentation are:

  • SEE have a relatively long history and can affect all semiconductor devices.
  • SEE arise from environmental radiation and present a variety of undesired behaviors.
  • SEE mitigation is possible and SEE susceptibility can be measured.

    After this presentation, attendees will have general familiarity with radiation effects in semiconductor devices. With this background, they will be primed for the presentations that follow during the day.
  • 8:15 AM (PT) On-Site Registration — Coffee, tea
    Eric Prebys, UC Davis The Crocker Nuclear Laboratory (30 minutes) In the 1960s, the magnetic return yoke and pole pieces from Ernest Lawrence’s 1939 60″ cyclotron were moved to UC Davis, where they formed the basis of the significantly upgraded 76″ Crocker Nuclear Laboratory Cyclotron, which first took beam in 1966 and is still operating today. The Crocker Cyclotron can accelerate species up to alpha particles at variable energies up to a maximum of 67.5 MeV for protons. Over the years, a wide variety of research has been done at the cyclotron, including some very interesting environmental studies. Currently, the cyclotron is used to treat eye cancer for one week each month, and the rest of the time is primarily used for radiation effects studies, for which the lab charges an hourly rate. Recently, the university has made a new commitment to the cyclotron, in the hopes of expanding the research and educational program, in addition to improving service to our commercial customers. This talk will summarize the history and status of the cyclotron, as well as current plans for the future. It’s also hoped to solicit input from the community about potential improvements to the facility.
    Joe Hupcey, Mentor The Crocker Nuclear Laboratory (30 minutes) Developing high-reliability FPGA designs demands mitigating single-event upsets (SEUs). A significant amount of effort is devoted to planning and designing SEU protection logic, but validation and testing of this protection is often limited. Functional simulation techniques provide some level of confidence but it is not exhaustive and extraordinarily time consuming. Code reviews and manual analysis of SEU protection often misses issues and is not an automated approach. Wouldnโ€™t it be great if there was a technology that would exhaustively test this logic in an automated way? Luckily, there is! Formal verification techniques and Sequential Logical Equivalency Checking (SLEC) can be used to exhaustively prove SEU mitigation logic for all configurations and state space. In this session we give an overview of these techniques and their application to fully verify SEU protection logic.
    Paula Chen, Xilinx 64 MeV Proton Single-Event Evaluation of Xilinx 20nm DDR4-IO Design (30 minutes) The single-event upset response of a customer memory interface design implemented in a Xilinx 20nm XCKU040 Field Programmable Gate Array (FPGA) is presented. Furthermore, a methodology to estimate designs FIT is discussed & validated using high energy protons.
    Vinod Ambrose, Intel Soft Error Rate Measurements in Solid State Drives (30 minutes) While the flash media in Solid State Drives (SSD) are not vulnerable to particle-induced SEU, there are other components, like the controller, that are vulnerable. Not a lot of measurements have been made on SEU vulnerabilities in SSDs. Measurement results are presented that show large SEU rates resulting in surprisingly high Silent Data Corruption (SDC) and Detected Unrecoverable Errors (DUE) unless careful consideration is given to SSD design. Results include alpha and neutron data for current generation datacenter and client SSDs from Intel and other manufacturers.
    Robert Baumann, Radiosity Solutions Making the Grade: From COTS to Space-grade Electronics (40 minutes) Small satellites are the most rapidly growing space sector due to their shorter development cycles, smaller-scale development teams, and reduced fabrication and launch costs. Many of these small-sat projects are being driven by relatively new (to space) commercial “players” who favor using Consumer-off-the-Shelf (COTS) over higher quality and more reliable space-grade components. After a brief review of the space environment and the types of chronic and instantaneous radiation effects that it can induce, we consider unintentional radiation performance enhancements gained as a natural consequence of technology scaling as well as some examples of targeted solutions for space-grade electronics. We also provide a couple of sobering real-world examples of how normal manufacturing variation in COTS can potentially lead to space mission failures. After a considering the quality, material, and test-coverage differences between the different grades from COTS to space-grade, we conclude with some observations about the suitability of each space grade in the rapidly evolving space market.
    Sang Hoon Jeon, HanYang University Logic Upsets in DDR4 SDRAMs Using 480 MeV Protons (30 minutes) In this technical presentation, a soft error study on logic upset in control logic is presented using a 480 MeV proton beam on commercial DDR4 SDRAM components from two different manufacturers. Soft error in logic is critical as logic portion of DRAM designs occupy larger real estate inside a chip and technology down-scaling decreases the critical charge. Also, one single-event upset in the logic part of SDRAM can cause thousands of bit flips that result in catastrophic failures. Moreover, some of the upset event in the control logic was not cleared by many read and write operations. Comparative study against DDR3 SDRAMs shows that DDR4 had 45% higher single bit upset (SBU) cross-section than DDR3. What is more, to understand how the storage capacitance of down-scaling DDR technologies affects soft error, soft error bits were compared to retention weak bits. No evidence was found that indicated that retention weak bits were more sensitive to soft error.
    Chamkaur Ghag, University College London Ultra-Low Background Radioassay Facilities at the Boulby Underground Laboratory (30 minutes) The UK’s Boulby Underground Laboratory, located 1100 m underground, operates cleanrooms for the operation of rare-event search experiments as well as unique radio-assay facilities for the screening campaigns necessary in constructing such experiments. The facility now hosts 7 ultra-low background gamma spectroscopy detectors, including the world’s most sensitive at low energies, crucial for the direct assay of Pb-210. The facility also hosts an XIA UltraLow-1800 in the same location and as such we are able to probe both bulk and surface radon daughter contamination in materials down to unprecedented levels. Our radio-assay facilities at Boulby are complemented by our world-class mass spectrometry (ICP-MS) and radon emanation measurement facilities at University College London. With our ICP-MS facility we achieve less than 10 parts per trillion (g/g) sensitivity to U238 and Th232, with turnaround of less than a day, using leading microwave digestion infrastructure to rapidly assess almost any material. Our radon facility can assay materials down to emanation rates of 0.1 mBq of Rn222, in large volume chambers for any material type. This talk shall present these facilities and the opportunities for radio-assays of materials of relevance to the electronics and advanced materials sectors using a complete suite of in-house ultra-low background techniques currently deployed for world-leading science applications and now available also for industry.
    Y. Sawada, MMC Development of High-Precision and Sensitive 2ฯ€ Gas Flow-Type Alpha Particle Counter (30 minutes) Along with the high-density integration of semiconductors in recent years, the requirement of alpha count for electronic materials such as solder have become stricter. Recently, some manufacturers demand 0.001cph/cm2, which is lower than the current highest grade of 0.002cph/cm2. In order to accurately measure the alpha count of ultra-low alpha materials, an extended time for measurement is necessary using a low background counter. In the case of the current background level (3 to 4cph), measurement becomes possible when the limit of detection drops to the necessary level, which requires a measurement time of 100 hours or longer. However, since the limit of detection hardly changes when measured at 100 hours or longer, specs less than 0.001cph/cm2 can’t be handled at the current background level. By dropping the background, the limit of detection decreases, which leads to an improvement in accuracy. We developed a new counter (gas flow proportional type) with a background level of around 1cph. As a result, the limit of detection decreased, improving the accuracy and sensitivity of the counter. Additionally, due to the decrease in background, the time required to reach the necessary level for 0.001cph/cm2 measurement halved compared to the conventional counter.
    Paul Muller, IBM Multi Bit Upset Mitigation Using the Fall Off Curve (30 minutes) Energetic particles and radiation can negatively impact silicon-based electronics, e.g. high doses of X-Rays or energetic neutrons can cause threshold voltage shifts for a multitude of transistors. Even a single particle which usually impacts only a single memory cell (Single Event Upset, SEU), can – under specific conditions – impact a multitude of cells. In such case we talk of a multi cell upset (MCU). For this to happen, the particle needs to travel in the plane of the active silicon over a distance which covers a multitude of cells. We are showing results of a proton beam experiment where this happens over a distance of up to 14 micrometers. A subset of the MCUs are multi cell upsets in one specific direction, namely the direction of the word line. These are called multi bit upsets (MBUs). While multi cell upsets in all other directions are easily detected and corrected, multi cell upsets in the direction of the word line are not, e.g. parity protection will fail for all even numbers of upsets. And error correction code (ECC) in the form of single error correct, double error detect (SEC-DED) fails to correct when two cells are upset, and starts failing to detect when three cells are upset.
    For these reasons, special attention needs to be paid to multi bit upsets (MBUs). The probability that besides a first cell, any additional cells on the same word line get upset, falls off quickly with increased physical distance. This probability can be shown for a variety of technology generations in a common Fall Off Curve. Besides the physical distance, the pattern of the stored data (checker board vs. alternating columns vs. all zero vs. all one, etc.) plays also a role. Interleaving is a technique to generate more SER robust array designs by increasing the physical distance between two cells protected by the same ECC word. This is achieved by interposing one or more cells protected by a different ECC word in between these two cells. If one cell is interposed, we talk about 2:1 interleaving, if three cells are interposed, we talk about 4:1 interleaving, and so on. The higher the interleaving ratio, the longer the physical distance between sensitive nodes, and thus the lower the probability of an MBU. The resulting designs are several orders of magnitude more MBU resilient. Thus, interleaving is a powerful tool to generate SER robust designs, and an alternative to more aggressive correction codes like double error correct, triple error detect (DEC-TED) codes or symbol ECC.
    Balaji Narasimhan, Broadcom Soft Errors: From Technology Trends to System-Level Performance (30 minutes) Technology scaling trends in the soft error rate (SER) of SRAMs from planar to FinFET process nodes are presented. While scaling from planar to the first FinFET process provided a large reduction in per-bit SER, the subsequent scaling within FinFET process nodes results in SER reduction comparable to per-bit cell area reduction. On the other hand, FinFET processes show a strong exponential increase in the SER with reduction in bias, compared to a linear bias dependence for the planar process. Implications of these results from system-level perspective are discussed. System-level SER test results for gigabit Ethernet transceiver devices are compared with estimates based on the technology SER data. Results indicate that most SEUs cause benign packet errors which are recoverable while the SER for more severe link-drop type events is significantly lower than estimates for this application. The talk highlights the importance of understanding the technology trends in SER as well as the true impact of soft errors from system perspective considering the intended product application.
    Mark Hanhardt, Sanford Underground Research Opportunities at Sanford Underground Research Facility (30 minutes) The Sanford Underground Research Facility provides an extremely low-background environment for conducting world-leading science experiments. An overview of the experiments and relevant fields of science will be presented. SURF has potential to house many additional experiments and welcomes applications from interested research/testing groups.
    Krishna Mohan, GlobalFoundries Demonstration of Soft Error Rate Robustness with Process Improvements and Material Changes – Case Studies (30 minutes) More often semiconductor foundry customers have more stringent Soft Error Rate (SER) radiation test reliability needs to meet either their end customers or their own product specific field applications’ stretched and stringent requirements. This was clearly evident especially in matured micron to sub-micron nodes where the SER requirements for foundry technology qualification were of 1000 to 2000 FITs/Mb aligned with ITRS Roadmap. This paper presents process studies on such cases where by foundry used Process Improvements and material changes implemented to achieve >50% to 2 order improvements on SER robustness on two of the technology nodes.
    Phil Oldiges, IBM Physics-Inspired Spreadsheet Models for Latch and SRAM SER Screening (30 minutes) (summary to be added)
    4:30 PM (PT) Close of Workshop

    Edge Computing and Artificial Intelligence: What Electronics Packaging Engineers Need to Know ๐Ÿ—“ ๐Ÿ—บ

    — edge computing, AI, connections, high-density packaging, challenges, opportunities …

    Speaker: Mudasir Ahmad, Distinguished Engineer/Senior Director, Cisco Systems, Inc.
    Meeting Date: Wednesday, October 10, 2018
    Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM Presentation
    Presentation-only: 12:00 noon (come at 11:45)
    Cost: $10 IEEE members, students, unemployed (free, for first 30); $15 non-members (free, for first 30)
    Location: SEMI International, 673 S Milpitas Blvd, Milpitas (use side entrance)
    Reservations: 1810eps.eventbrite.com
    Summary: Advanced Networking Technology has been the key driver of internet traffic over the past two decades. It has spearheaded the prevalence of smartphones, big data, voice and video. The challenges and opportunities for advanced packaging in Networking Applications, IoT, Edge Computing and Artificial Intelligence will be outlined.
    Networking is now driving the exponential growth of Internet of Things (IoT) — more devices and machines connected to each other and the internet. Key to delivering the IoT ecosystem is Edge Computing. As more devices are connected to each other, the latency and bandwidth of the connections between the devices becomes a critical bottleneck. Edge computing strives to balance the need for faster connectivity with the cost, resilience and scalability challenges of hyper-connected devices. In addition to enabling IoT, Networking is also driving the incorporation of Artificial Intelligence (AI) into IoT devices and in the network itself. AI is helping networks connect, repair and defend themselves, ensuring speed, scalability and security. In this talk, the key trends and challenges in Networking as they relate to IoT, Edge Computing and Artificial Intelligence will be presented, with a focus on packaging.

    Bio: Mudasir Ahmad is a Distinguished Engineer/Senior Director at Cisco Systems, Inc. He has been involved with mechanical design, microelectronics packaging design and reliability analysis for 17 years. He received his M.S. in Management Science & Engineering at Stanford University, his M.S. degree in Mechanical Engineering from Georgia Institute of Technology and his Bachelors from Ohio University.
    Mudasir is leading the Center of Excellence for Numerical Analysis, developing new analytical/stochastic algorithms, experimental design, thermal and reliability characterization of next generation 3D packaging, System-in-Package Modules and Silicon Photonics. Mudasir is also involved with implementing IoT, Artificial Intelligence and Big Data Analytics to streamline Supply Chain Operations. Mudasir has delivered several invited talks on leading technology solutions internationally.
    Outside of Cisco, he is involved with programs at the Silicon Valley Chapter of the Electronics Packaging Society of the IEEE (EPS), and actively participates in IPC and JEDEC standards organizations. He was actively involved in the local EPS chapter of IEEE for several years, holding the positions of Secretary, Vice Chair and Chair of the Chapter.
    Mudasir has over 30 publications on microelectronic packaging, two book chapters, and 13 US Patents. He received the internationally renowned Outstanding Young Engineer Award in 2012 from the IEEE.

    Tour of Nvidia’s Space-Age Showroom and Technology ๐Ÿ—“

    — tour, review of Nvidia product line …

    Speaker: Dongji Xie, Nvidia
    Meeting Date: Friday, September 7, 2018
    Time: 12:00 Noon: Talk/tour (no food served)
    Cost: none; limited to students and IEEE Members only (30 max)
    Location: near San Tomas and Central Expressway, Santa Clara (details will be sent to registrants)
    Reservations: 1809eps.eventbrite.com
    Summary: (not available)

    Flexible Hybrid Electronics: System as Package (& Tour) ๐Ÿ—“

    — forecasts, IoT implementation, additive processing, flex substrate, low cost, applications, plus tour …

    Speaker: Wilfried Bair, VP-Engineering, NextFlex
    Meeting Date: Thursday, August 23, 2018
    Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 – 2:00 PM Presentation and Tour
    Cost: $10 IEEE members, students, unemployed; $15 non-members (includes sandwich lunch)
    Location: 2244 Blach Place # 150, San Jose
    Reservations: 1808eps.eventbrite.com
    Summary: According to an IEEE Spectrum report released in 2016, the connected Internet of Things world was, at the time, forecasted to consist of about 30 billion objects by 2020. This number is reduced from the 50 billion connected devices by 2020 forecast in 2010 by Ericsson and Cisco, and from the forecast of one trillion connected devices by 2020 by IBM in 2012. An underlying premise of the successfully connected IoT object world is that those devices are low cost and ubiquitous so that they can be easily deployed, and devices lacking these crucial factors have created a barrier against widespread IoT adoption. Flexible hybrid electronics (FHE) address these issues with two unique factors that traditional technology cannot provide: it uses additive processing to reduce manufacturing cost; and enables placement of devices on conformal, flexible or stretchable surfaces at low cost. Examples for industrial, medical, automotive and consumer markets will show how additive manufacturing, combined with flexible substrates, can deliver on the promise of the “electronics on everything.”

    Bio: Wilfried holds advanced degrees in Manufacturing and Production Planning Systems, Organizational Development, and International Marketing from the University of Linz in Austria. He is Vice President of Engineering at NextFlex.

    10th Annual IEEE EPS SCV Soft Error Rate (SER) Workshop ๐Ÿ—“

    — alpha upset, materials selection, process control, tutorial, test facilities, case studies …

    Date: Wednesday, October 24, 2018
    Time: 8:30 am – 4:30 pm (PT) (Lunch will be provided)
    Location: Xilinx, 2100 All Programmable Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
    Attendance: On-site or Remote (WebEx)
    Cost: none
    Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.

    Our annual IEEE Soft Error Rate Workshop will enter its 10th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
    For this year’s event, we will continue with the format used in the previous two years, with invitied industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
    (All times shown are Pacific Daylight Time, California)

    Time (PDT) Presenter Title
    8:15 AM Check-in and Registration WebEx: Login information will be sent to registrants on Monday, October 22.
    8:35 AM Paul Muller, IBM Multi Bit Upset Mitigation Using the Fall Off Curve (more)
    9:05 AM Chamkaur Ghag, University College London Ultra-Low Background Radioassay Facilities at the Boulby Underground Laboratory (more)
    9:35 AM Joe Hupcey, Mentor Exhaustively Verify EDAC Protected State Machines and Memories Using Formal Verification (more)
    10:15 AM Paula Chen, Xilinx 64 MeV Proton Single-Event Evaluation of Xilinx 20nm DDR4-IO Design (more)
    10:45 AM Sang Hoon Jeon, HanYang University Logic Upsets in DDR4 SDRAMs Using 480 MeV Protons (more)
    11:15 AM Robert Baumann, Radiosity Solutions Making the Grade: From COTS to Space-grade Electronics (more)
    12:15 – 12:45 PM Lunch and Discussions (Lunch will be provided)
    12:45 PM Eric Prebys, UC Davis The Crocker Nuclear Laboratory (more)
    1:15 PM Mark Hanhardt, Sanford Underground Research Opportunities at Sanford Underground Research Facility (more)
    1:45 PM Krishna Mohan, GlobalFoundries Demonstration of Soft Error Rate Robustness with Process Improvements and Material Changes – Case Studies (more)
    2:15 PM Balaji Narasimhan, Broadcom Soft Errors: From Technology Trends to System-Level Performance (more)
    3:00 PM Y. Sawada, MMC Development of High-Precision and Sensitive 2? Gas Flow-Type Alpha Particle Counter (more)
    3:30 PM Phil Oldiges, IBM Physics-Inspired Spreadsheet Models for Latch and SRAM SER Screening (more)
    4:00 PM Vinod Ambrose, Intel Soft Error Rate Measurements in Solid State Drives (more)
    4:30 PM Close of Workshop

    View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations

    Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, October 22.

    Eric Crabill, Xilinx (Chair)
    Peng Su, Juniper Networks
    Rick Wong, Charlie Slayman, Cisco Systems, Inc.
    K. Paul Muller, IBM
    Norbert Seifert, Intel
    Shomir Dighe, Paul Wesling, Santa Clara Valley EPS Chapter
    Vijay Narasimhan, Jin-woo Han, Santa Clara Valley EDS Chapter

    Contact us: 2018 SER Workshop

    2D to 3D Package Architectures: Back to the Future ๐Ÿ—“ ๐Ÿ—บ

    — scaling, heterogeneous integration, impact on power, performance, latency, nomenclature for package architectures, current metrics, projections …

    Speaker: Dr. Raja Swaminathan, Package Architect
    Presentation Slides: “2D to 3D Package Architectures: Back to the Future” (1.5 MB PDF)
    Meeting Date: Thursday, May 3, 2018
    Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
    Presentation-only: 12:00 noon (come at 11:45)
    Cost: $5 IEEE members, students, unemployed; $10 non-members

    Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
    Reservations: (URL) 1805aeps.eventbrite.com
    Summary: Moore’s Law Scaling has driven electronics industry growth and new package architectures (including 3D architectures and architectures currently defined as 2.1D, 2.3D or 2.5D architectures) are projected to be major enablers to maintain the pace of Moore’s law scaling and enable heterogeneous integration. Historically, packaging has scaled sufficiently to act as a space and electrical transformer to enable transistor/silicon scaling, and innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. With an increasing drive for heterogeneous integration, packaging is being increasingly challenged to deliver power-efficient, high bandwidth on/off package low power links and meet diverse functionality ranging from high performance servers to flexible, wearable electronics. This talk will introduce a new IEEE standardized industry nomenclature on package architectures covering and clearly demarcating both 2D and 3D constructions, as well as highlight the key metrics driving the evolution of these architectures, their current values (based on the state of the art) and projections for the next 5-10 years. This is expected to drive focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next generation requirements in the 2D-3D architecture space.

    Bio: Dr. Raja Swaminathan is an IEEE senior member and was a package architect at Intel for next generation server, client and mobile products. His expertise is on delivering integrated HVM-friendly package architectures with optimized electrical, mechanical, and thermal solutions. He is an IEEE, ITRS and iNEMI Roadmap author on packaging and design, and recently drove industry convergence of 2D and 3D architecture nomenclatures and design, process and electrical metrics. He has also served on IEEE micro-electronics and magnetics technical committees and has been key note speaker in electronics conferences. He has 26 patents and 25 peer-reviewed publications and holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University.