Advanced Packaging Trends & Electronic Materials in Era of Digital Transformation 🗓 🗺

— integration technologies, new applications, trends in 5G, Artificial Intelligence, IoT, autonomous driving …

Speaker: Rozalia Beica, ­ Global Director Strategic Marketing, Electronics & Imaging Division, DuPont
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Meeting Date: Friday, June 28, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1906eps.eventbrite.com
Summary: Digital transformation is further expanding into new markets bringing new application opportunities and driving increased adoption of electronics and semiconductor devices. The explosion of new applications is driving the semiconductor industry to transition from a technology node to an application driven industry. While advancing the technology node continues, new architectures and integration technologies are being developed to address increasing market requirements and the need of integrating more functionalities within smaller and more compact systems. A wide range of packaging technologies have already been successfully developed and adopted in the industry enabling single and multi-die packaging. While these technologies will continue to grow and further evolve, heterogeneous integration is gaining a lot of interest in the industry due to several benefits it can bring. This will also drive the need for more performing electronic materials and processes.
The presentation will provide an overview of the major trends (5G, Artificial Intelligence, IoT, Autonomous Driving, etc.) driving the semiconductor and packaging industry. The talk will highlight the various packaging platforms and their evolution as well as the material and processing challenges and needs driven by these applications.


Bio: Rozalia Beica is Global Director Strategic Marketing, DuPont, Electronics & Imaging Division. In her current role, Rozalia leads strategic marketing activities across Electronics & Imaging Division. She has 27 years of international working experience across various industries, including industrial, electronics and semiconductors. For 20 years she was involved in the research, applications and strategic marketing of Advanced Packaging technologies, with global leading responsibilities at specialty chemicals (Rohm and Haas Electronic Materials), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining DuPont, Rozalia was the CTO of Yole Développement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing.
Throughout her career, Rozalia has been actively supporting industry activities worldwide: Program Director of EMC3D Consortia, General Chair of IMAPS Device Packaging and Global Semiconductor and Electronics Forums, Technical Advisory Board Member at SRC, Member of the Executive Committee of ECTC, IMAPS SiP, ISQED, ESTC and member of several committees worldwide (ITRS, IWLPC, EPTC and EPS). Current industry involvements include: IMAPS VP of Technology, Technical Chair IMAPS Advanced SiP USA and SiP China Symposium, ECTC Assistant Program Chair, HIR WLP Chair, Advisory Board Member of 3DinCites and IMPACT Taiwan. She has over 150 presentations and publications (including 3 book chapters on 3D IC technologies), several keynotes, invited presentations and panel participations.
Rozalia has a M.Sc. in Chemical Engineering from Polytechnic University “Traian Vuia” (Romania), a M.Sc. in Management of Technology from KW University (USA), and a Global Executive MBA from Instituto de Empresa Business School (Spain).

3D X-ray Characterization; High Density Hybrid Bonding for 2.5D/3D Applications 🗓 🗺

— chip-stacking, microbumps, issues, new process, low cost, sensors, MEMS, computing …

12:00 – 12:30: “Non-Destructive Characterization of Advanced IC Packages with Buried Features using 3D X-ray”
Speaker #1: Thom Gregorich, Carl Zeiss PCS Inc.
12:30 – 1:15: “High Density D2W DBI Hybrid Bonding for 2.5D/3D Applications”
Speaker #2: Dr. Sitaram Arkalgud, Xperi
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Meeting Date: Wednesday, April 10, 2019
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM First Presentation; 12:30 PM Second Presentation
Presentations-only: 12:00 noon (come at 11:45 or 12:15)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Co-sponsor: MEPTEC
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1904eps.eventbrite.com

First Talk Summary (Thomas Gregorich): For more than 40 years the semiconductor industry has been driven by silicon scaling: minimum CMOS feature size scaled from tens of microns down to a few nanometers. During the same period, minimum package feature size scaled much less, largely because it was more beneficial to scale the silicon than to scale the package. However, silicon scaling is slowing down and there are other challenges such as memory bandwidth and reliability which cannot be solved by silicon scaling. It is clear that package technology is being pushed out of its “comfort zone” and has entered an era of aggressive feature scaling and performance enhancement.
This presentation will explore the history of feature size scaling in wafer fabrication and the types of inspection and metrology systems which were developed to enable this scaling. Inspection and metrology process flows in wafer fabrication will be compared to inspection and metrology process flows in package assembly, and opportunities will be identified to enhance inspection and metrology systems in package assembly. The ZEISS Xradia Versa 620 X-ray Microscope and Measurement System will be introduced as a non-destructive solution to enhance package inspection and metrology during development and characterization, and several use cases will be presented.

Bio: Mr. Thomas Gregorich is Director of Business Development at ZEISS Semiconductor Manufacturing Technology where he is responsible for imaging products which support Advanced Packaging. Previously Mr. Gregorich held senior-level positions at Western Digital, Micron, Broadcom, MediaTek and Qualcomm. At Micron Mr. Gregorich qualified the Company’s first commercial TSV product. While at Qualcomm he established the Package Engineering department and for 12 years led the development of Qualcomm’s small form-factor package portfolio including NSP, CSP, BCC, QFN, POP and PIP. Prior to his position at Qualcomm, Mr. Gregorich worked for Motorola and had assignments in the Semiconductor Products Sector and Corporate Research, both in the United States as well as Japan, Taiwan and China. Mr. Gregorich has a BS in Mechanical Engineering from Bradley University, an MBA from Northern Illinois University and is a Senior Member of IEEE.

Second Talk Summary (Sitaram Arkalgud): Chip and wafer stacking have made major inroads into several semiconductor segments, including CMOS Image Sensors, MEMS and HPC. As stacking becomes a necessity, it continues to expand into DRAM, RF and other markets. Microbumps are today’s interconnect of choice, but they face issues of scalability and reliability, together with underfill and polyimide layers introducing thermo-mechanical issues which worsen with large dies. This talk describes a room-temperature hybrid bonding process that eliminates microbumps and associated organic layers, resulting in high reliability, low cost, and high density interconnects with improved thermo-mechanical performance. It will present our D2W DBI development work targeting 2.5D and 3D applications.

Bio: Sitaram Arkalgud is driving the application of Xperi bonding technologies (ZiBond® and DBI®) in numerous 3D products across the industry. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Xperi (Invensas), he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, Cu/Cu wafer/die bonding and wafer thinning for 3D ICs. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 45 U.S. patents. Sitaram holds Masters and Ph.D. degrees in Materials Engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a Bachelor’s degree in Metallurgical Engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.

Designing Plastic Parts for Multi-Jet Fusion vs Injection Molding + Tour 🗓 🗺

— tour, comparison, considerations, cost, schedule, quality, case study, HP Z3D camera …

Speaker: John Briden, Application Development Consultant, HP 3D Printing Group
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Meeting Date: Thursday, March 14, 2019
Time: Registration/snacks 6:00 PM; Lab Tour 6:30 PM; Presentation 7:00 PM
Cost: $10 general admission; $0 IEEE members (use IEEE member number)
Sponsor: ASME SF Bay Area Section
Location: H-P, 1501 Page Mill Road, Palo Alto
Reservations: www.eventbrite.com/o/asme-santa-clara-valley-section-484885605 (required; no walk-in’s)
Summary: This presentation will cover how the two technologies — Multi Jet Fusion (MJF) and Injection molding (IM) — work, with a more detailed explanation of MJF. The speaker will discuss the reasons for considering the use of MJF instead of IM based on a product development framework of cost, schedule, quality and unique value. He will use that framework for a more detailed comparison of the technologies. The presentation will highlight a specific case study that the speaker had direct personal experience with — the development of the HP Z3D Camera. There will be some sample parts of MJF to pass around.

Bio: John Briden is a Stanford Mechanical Engineering graduate who has spent a career developing products at leading consumer electronics companies like Apple and HP Inc. About a year and a half ago he joined HP’s Multi-Jet-Fusion 3D printing group to help usher in the next industrial revolution with 3D printing for production.

TI Coordinates:
TI Conference Center, Santa Clara
37.375686
-121.999004
SEMI coordinates:
SEMI World Hdqtrs, Milpitas
Lat: 37.427
Long: -121.8958

Sponsors Needed for STEM Internships for this Summer 🗓

— highschool tech students, funding, companies needed, summer workers, career development …

Your EPS chapter has voted to lend support to the Cupertino and Sunnyvale Rotary Clubs, which are working with the Fremont Union High School District to kick off a paid high school summer internship program for a select group of students at Fremont High School in Sunnyvale. The goal of the pilot is to increase interest in STEM careers by providing students with the opportunity to work side-by-side with engineers or technicians in a company and apply what they’ve learned from the Engineering Design Pathway course(s) they’ve completed. Rotary is looking for companies to either:

1. Provide paid internship opportunities (up to 10 internships). We have funding to cover 50% of the wage cost ($15/hour)for a 6-week, 20-hour per week internship. Companies would provide funding to cover the remaining 50% ($900 per internship for a 20-hour per week internship; or $1800 per internship if sufficient funding is obtained for 40-hour per week internship);

2. Provide financial support as a Program Sponsor (We need to raise $9000 to be able to offer students a 6-week, 40-hour per week, internship).

Note that Fremont Union High School District will have a 3rd Party who will take on the “Employer of Record” role, to handle the payroll services as well as the insurance to cover the students.

If your company is interested in participating in this initiative, please have them contact: Steve Onishi (Co-Chair, Workforce Development Committee, Cupertino Rotary) at steve.onishi@gmail.com or 408.621.4353.

Advanced Packaging: A Perspective on 2D and 3D Architectures 🗓 🗺

— heterogeneous integration, drivers, evolution, density, options, developments needed, scaling …

Speaker: Dr. Deepak Goyal, Director of the Assembly and Test Technology FA Labs, Intel register
Meeting Date: Thursday, February 7, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Reservations: 1902eps.eventbrite.com
Summary: Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems. HI is crucially enabled by advanced packaging, since packages are an optimal HI platform. This talk will address the role of advanced packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities. It will show how 2D and 3D packaging has evolved to provide increased interconnect density and how the different technology solutions available today meet the demands of diverse markets. Key high-end technologies such as EMIB, the silicon interposer and Foveros will be discussed in this context. The talk will also touch on the evolving future challenges in interconnect density scaling. In addition to interconnect scaling, this talk will also briefly discuss challenges and opportunities in key areas such as power management, high speed IO, thermal management, test and FI/FA.

Bio: Deepak Goyal graduated with a PhD from State University of New York, Stony Brook, and joined Intel as a Failure Analysis Engineer. He is currently the Director of the Assembly and Test Technology Development Failure Analysis Labs at Intel. His responsibilities include development of the next generation of analytical tools and techniques, defect characterization, fault isolation, failure and materials analyses for the next generation package technology development at Intel, analytical chemistry labs in support of the substrate development and manufacturing, and Board and System level failure analysis. He has helped with the development of all Intel assembly technologies including FCxGA, FCCSP, TSVs, EMIB and Foveros. He is an expert in the failure analysis of packages and has taught Professional Development courses on Package FA/FI methods and failure mechanisms at the Electronics Components and Technology Conference (ECTC) from 2003 to present. He has won two Intel Achievement Awards and 25 Division Recognition Awards at Intel. Deepak has authored and co-authored over 50 papers and holds 11 US patents with 5 more in flight. He has co-authored 2 book chapters and has co-edited a book titled “3D Microelectronic Packaging: From Fundamentals to Applications”. He is a senior member of the IEEE and was the chair of the Package and Interconnect Failure Analysis Forum sponsored by International Sematech. He is currently the chair of the ECTC Applied Reliability Committee.

Visualizing the Packaging Roadmap 🗓 🗺

— ITRS, Moore’s Law, innovation, roadmaps, packaging issues, hi-performance computing, solutions …

Speaker: Ivor Barber, Corporate VP for Packaging, AMD
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Presentation Slides: “Visualizing the Packaging Roadmap” (1.7 MB PDF)
Meeting Date: Wednesday, March 13, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE/MEPTEC members students, unemployed; $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Reservations: 1903eps.eventbrite.com
Co-sponsor:
Summary: With the end of Moore’s Law as an economic driver at 28nm, and publication of the final edition of the ITRS in July 2016, we find packaging is now on the center stage of semiconductor innovation — but what roadmap do we follow? This presentation will discuss prior roadmaps and how the packaging industry is responding with a product-based integrated solution roadmap. The presenter will discuss the goals of Heterogeneous Integration for High Performance Computing Applications and the packaging solutions this will drive.

Bio: Ivor Barber is currently Corporate VP for Packaging at AMD with responsibility for all Packaging activity from Design through High Volume Manufacturing. With over 35 years experience in the Semiconductor Industry, Ivor has held various Engineering and Management positions in Assembly, Package Characterization and Package Design at National Semiconductor, Fairchild Semiconductor, VLSI Technology, LSI Corporation and Xilinx. Ivor graduated from Napier University in Edinburgh, Scotland with a Bachelors degree in Technology and holds 15 US patents related to packaging.

Heterogeneous Integration Roadmap 2-Day Symposium 🗓 🗺

— 2nd Annual, intro to HIR v1.0, overviews, integration, working groups, participation …

register
Dates: Thursday, 21 February 2019 (8:30 AM – 6:00 PM) and Friday 22 February (8:30 AM – 4:00 PM)
Cost: $50 General Admission; $35 IEEE/ASME members and employees of SEMI member companies; $35 for students, unemployed, retired.

Location: SEMI International Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1902symp-eps.eventbrite.com

Program Outline: (details below)
Download Full Program, Hotel Recommendations
NOTE: No photographs or videos will be allowed during the Symposium. (This announcement complies with IEEE policies.)
Day 1: Introduction to HIR v1.0
— Release of HIR version 1.0: How to Download and Use the Roadmap
— Presentations from HIR Technical Working Group chairs
Day 2: TWG Breakout Sessions for HIR v2.0 (TWG Caucus & Cross-TWG meetings)

Sponsors:

We thank our financial supporters for 2019:
     



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.

A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity, and assembled a group of leading technical experts to develop this Roadmap. The first work product of the Roadmap team is being presented by the chairs of the 20 Technical Working Groups. This Version 1.0 is now being released, for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, 21 February 2019: Introduction to HIR v1.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00: Start of Program: Welcome – Ajit Manocha, President & CEO, SEMI Int’l
9:15 – 10:50 AM – Session 1 – Heterogeneous Integration for High Performance
                Chair: Bill Bottoms, EPS and 3MTS
    — High Performance Computing & Data Center, Kanad Ghose (Binghamton U), Dale Becker (IBM)
    — 3D and Interconnect, Ravi Mahajan (Intel)
    — Thermal Management, Madhu Iyenger (Google), Azmat Malik (Acuventures)
    — Integrated Photonics, Amr Helmy (U-Toronto), Bill Bottoms (3MTS)
    — WLP (fan-in and fan-out), Rozalia Beica (DOW), John Hunt (ASE)
    — Test, Dave Armstrong (Advantest)
BREAK
11:00 – 12:30 PM – Session 2 – Heterogeneous Integration for Consumer and Industrial Applications
                Chair: Subu Iyer, UCLA
    — Emerging Devices, Meyya Meyyappan (NASA Ames)
    — Medical, Health and Wearables, Mark Poliks (Binghamton U), Nancy Stoffel (GE), Benson Chan (Binghamton U)
    — SiP & Modules, Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon)
    — Single Chip and Multi Chip Integration, William Chen (ASE), Annette Teng (Promex)
    — Integrated Power Packaging, Patrick McClusky (UMD), Doug Hopkins (NCSU)
    — IoT, Robert Lo (ITRI Taiwan)
12:30 PM – Hosts Recognition; Symposium Sponsor Thank You
12:40 – 1:40 PM – LUNCH     (discussions; box lunch included)
1:40 – 2:25 PM – PLENARY PRESENTATION
Invited Speaker: Babak Sabi, Corporate Vice President, General Manager of Assembly & Test Development, Intel Corporation
2:25 – 3:45 PM -Session 3 – Heterogeneous Integration for Special Applications
                Chair: Tom Salmon, SEMI
    — Aerospace and Defense, Tim Lee (Boeing)
    — 5G in RF and Analog Mixed Signal, Tim Lee (Boeing), Herbert Bennett (Alta Tech)
    — Cyber Security, Sohrab Aftabjahani (Intel)
    — Simulation, Richard Rao (Microsemi), Chris Bailey (U-Greenwich), Xuejun Fan (Lamar U)
    — Co-Design, Jose Schutt-Aine (U of Illinois)
    — MEMS and Sensor Integration, Shafi Saiyed (ADI)
BREAK
4:00 – 5:15 PM – Session 4 – Heterogeneous Integration Applications, Materials & Simulation
                Chair: Amr Helmy, Univ of Toronto
    — Automotive, Urmi Ray (STATS ChipPAC), Rich Rice (ASE)
    — Mobile, William Chen (ASE)
    — Materials and Emerging Research Materials, Bill Bottoms (3MTS)
    — Supply Chain, Tom Salmon (SEMI)
5:15 PM – Information on Release of HIR version 1.0; Download & Roadmap Use
5:30 PM – WRAP UP: Nicky Lu, CEO and Chairman, Etron Technology Inc.
5:45 – 6:45 PM Reception, Social
Wine-tasting and sampling many fine wines from Napa Valley with bartender John Friedlund

Friday, 22 February 2019: TWG Breakout Sessions for HIR & Open House v2.0
Who should attend: All HIR Technical Working Group members and anyone interested in participating or learning more about the Heterogeneous Integration Roadmap and participating in interaction, collaboration and feedback.
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30: Registration and refreshments
9:00: HIR Business:     — Completion of manuscript: Full Roadmaps & White Papers     — HIR 1.0 Release plan     — Peer Review     — Chapters Complete     — Download Schedules     — Planning for HIR 2.0     — 2019 Events: ECTC Las Vegas, SEMICON West, Asia, Europe
10:30: Breakout Sessions A and B, TWG Exchange Caucuses
Lunch (box lunches provided)
1:00 PM – Breakout Sessions C and D, TWG Exchange Caucuses
2:30 PM – Wrap-Up

System Assembly using a Microchip Printer 🗓 🗺

— chiplets, electrostatic assembly, sort, transport, roll-based, planarization, interconnect, HI …

Speaker: Eugene Chow, PARC
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Meeting Date: Thursday, January 24, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1901eps.eventbrite.com
Summary: We aim to develop a system which can rapidly assemble small semiconductor chips (<1mm) into electronic systems. The process uses chips initially in solution, and then sorts, transports, and orients chips with directed electrostatic assembly with open- and closed-loop control. Assemblies are then transferred to final substrates with a stamp or continuous feed roll-based method, and then electrically interconnected. The current laboratory systems have handled small chips (10um-500um) and demonstrated fine registration (<1um and <1°). Ultimately, massively parallel automated microassembly, analogous to a xerographic printer using microchips instead of toner, could be used for integrating circuits, microLEDs and other semiconductor components into complex, heterogeneous systems.
Bio: Dr. Eugene Chow is a principal scientist and manager of the microsystems research group at PARC (a Xerox Company). The group works on novel printing-related processes, electronics and biomedicine. In the advanced electronics packaging area he focuses on lithographically defined microspring flip chip interconnects for integrated test, rework and packaging, and automated chiplet assembly. He leads research projects at PARC with support from Xerox, other companies and the government, and has ~100 patents granted/filed. He earned a B.S. from UC Berkeley in engineering physics, and did graduate work at Stanford University (MS engineering management, MS and PhD in electrical engineering).

TI Coordinates:
TI Conference Center, Santa Clara
37.375686
-121.999004

Holistic Design in Optical Interconnects 🗓 🗺

— high-performance, bandwidths, power budget, low-cost approaches, photonics co-design …

Speaker: Dr. Azita Emami, Professor, California Institute of Technology, and IEEE-SSCS Distinguished Lecturer
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Meeting Date: Thursday, December 6, 2018
Time: 6:00 PM Networking and refreshments; 6:30 PM Presentation
Cost: Free, donation is accepted for refreshments: $2 IEEE members/$5 non-members, pay online or at the door

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-sscs/upcoming-events
Summary: The scalability of CMOS technology has driven computation into a diverse range of applications across the power-consumption, performance and size spectra. Today, Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large-scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular, effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.


Bio: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

Enabling System Performance through Practical Thermal Innovation

Speaker: (name, affiliation)
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Presentation Slides: “title” (xx MB PDF) after meeting
Meeting Date: (day), January xx, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1901eps.eventbrite.com
Summary: There are tremendous challenges of increasing total power as well as high localized heat flux resulting from the growing push for heterogeneous integration on silicon and at the package level.
These challenges dictate that a thermal solution needs to be architected based on these factors: current density; power mapping; package structure; and assembly and reliability requirements.
This talk will explore the impact of selected thermal solutions at the packaging and assembly levels, as well as at the system level. It will emphasize how to co-design the thermal architecture with performance, reliability, mechanical and assembly requirements. We focus on having a full understanding of the end-user application. Also, this talk will disclose an innovative thermal solution that can extend the cooling limit by up to 50%.


Bio: Dr. Gamal Refai-Ahmed is a technical director at Xilinx, in San Jose. He is an ASME Life Fellow, a Fellow of the Canadian Academy of Engineering, and a Distinguished Engineer (and Adjunct Professor) at SUNY Binghamton. He obtained the M. A. SC. and Ph. D. degrees in Mechanical Engineering from the University of Waterloo. Gamal has made important contributions to electronics packaging and development of electronics cooling technologies for the consumer electronics, telecommunications and energy industries. He is the author of more than 90 technical papers and more than 100 US patents/International Patents/Pending patents.
Gamal is an Associate Editor of the IEEE/EPS Transactions on Components, Packaging and Manufacturing Technology, and the ASME Journal of Thermal Sciences and Engineering and Applications. He is the recipient of the 2008 Dxcellent Thermal Management award, 2010 Best Associate Editor J Electronics Packaging, 2010 Calvin Lecture and 2013 K16-Clock award in recognition for his scientific contributions and leadership in promoting best electronics packaging engineering practices. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation, the 2015 ASME service award and the 2016 IEEC SUNY-Binghamton Innovation leader of the year.