Sponsors Needed for STEM Internships for this Summer 🗓

— highschool tech students, funding, companies needed, summer workers, career development …

Your EPS chapter has voted to lend support to the Cupertino and Sunnyvale Rotary Clubs, which are working with the Fremont Union High School District to kick off a paid high school summer internship program for a select group of students at Fremont High School in Sunnyvale. The goal of the pilot is to increase interest in STEM careers by providing students with the opportunity to work side-by-side with engineers or technicians in a company and apply what they’ve learned from the Engineering Design Pathway course(s) they’ve completed. Rotary is looking for companies to either:

1. Provide paid internship opportunities (up to 10 internships). We have funding to cover 50% of the wage cost ($15/hour)for a 6-week, 20-hour per week internship. Companies would provide funding to cover the remaining 50% ($900 per internship for a 20-hour per week internship; or $1800 per internship if sufficient funding is obtained for 40-hour per week internship);

2. Provide financial support as a Program Sponsor (We need to raise $9000 to be able to offer students a 6-week, 40-hour per week, internship).

Note that Fremont Union High School District will have a 3rd Party who will take on the “Employer of Record” role, to handle the payroll services as well as the insurance to cover the students.

If your company is interested in participating in this initiative, please have them contact: Steve Onishi (Co-Chair, Workforce Development Committee, Cupertino Rotary) at steve.onishi@gmail.com or 408.621.4353.

Advanced Packaging: A Perspective on 2D and 3D Architectures 🗓 🗺

— heterogeneous integration, drivers, evolution, density, options, developments needed, scaling …

Speaker: Dr. Deepak Goyal, Director of the Assembly and Test Technology FA Labs, Intel register
Meeting Date: Thursday, February 7, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Reservations: 1902eps.eventbrite.com
Summary: Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems. HI is crucially enabled by advanced packaging, since packages are an optimal HI platform. This talk will address the role of advanced packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities. It will show how 2D and 3D packaging has evolved to provide increased interconnect density and how the different technology solutions available today meet the demands of diverse markets. Key high-end technologies such as EMIB, the silicon interposer and Foveros will be discussed in this context. The talk will also touch on the evolving future challenges in interconnect density scaling. In addition to interconnect scaling, this talk will also briefly discuss challenges and opportunities in key areas such as power management, high speed IO, thermal management, test and FI/FA.

Bio: Deepak Goyal graduated with a PhD from State University of New York, Stony Brook, and joined Intel as a Failure Analysis Engineer. He is currently the Director of the Assembly and Test Technology Development Failure Analysis Labs at Intel. His responsibilities include development of the next generation of analytical tools and techniques, defect characterization, fault isolation, failure and materials analyses for the next generation package technology development at Intel, analytical chemistry labs in support of the substrate development and manufacturing, and Board and System level failure analysis. He has helped with the development of all Intel assembly technologies including FCxGA, FCCSP, TSVs, EMIB and Foveros. He is an expert in the failure analysis of packages and has taught Professional Development courses on Package FA/FI methods and failure mechanisms at the Electronics Components and Technology Conference (ECTC) from 2003 to present. He has won two Intel Achievement Awards and 25 Division Recognition Awards at Intel. Deepak has authored and co-authored over 50 papers and holds 11 US patents with 5 more in flight. He has co-authored 2 book chapters and has co-edited a book titled “3D Microelectronic Packaging: From Fundamentals to Applications”. He is a senior member of the IEEE and was the chair of the Package and Interconnect Failure Analysis Forum sponsored by International Sematech. He is currently the chair of the ECTC Applied Reliability Committee.

Visualizing the Packaging Roadmap 🗓 🗺

— ITRS, Moore’s Law, innovation, roadmaps, packaging issues, hi-performance computing, solutions …

Speaker: Ivor Barber, Corporate VP for Packaging, AMD
register
Meeting Date: Wednesday, March 13, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Reservations: 1903eps.eventbrite.com
Summary: With the end of Moore’s Law as an economic driver at 28nm, and publication of the final edition of the ITRS in July 2016, we find packaging is now on the center stage of semiconductor innovation — but what roadmap do we follow? This presentation will discuss prior roadmaps and how the packaging industry is responding with a product-based integrated solution roadmap. The presenter will discuss the goals of Heterogeneous Integration for High Performance Computing Applications and the packaging solutions this will drive.

Bio: Ivor Barber is currently Corporate VP for Packaging at AMD with responsibility for all Packaging activity from Design through High Volume Manufacturing. With over 35 years experience in the Semiconductor Industry, Ivor has held various Engineering and Management positions in Assembly, Package Characterization and Package Design at National Semiconductor, Fairchild Semiconductor, VLSI Technology, LSI Corporation and Xilinx. Ivor graduated from Napier University in Edinburgh, Scotland with a Bachelors degree in Technology and holds 15 US patents related to packaging.

Heterogeneous Integration Roadmap 2-Day Symposium 🗓 🗺

— 2nd Annual, intro to HIR v1.0, overviews, integration, working groups, participation …

register
Dates: Thursday, 21 February 2019 (8:30 AM – 6:00 PM) and Friday 22 February (8:30 AM – 4:00 PM)
Cost: $40 General Admission; $25 IEEE/ASME members and employees of SEMI member companies; $25 for students, unemployed, retired.   ($10 more, after Feb. 8th)

Location: SEMI International Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1902symp-eps.eventbrite.com

Program Outline: (details below)
Download Full Program, Hotel Recommendations
Day 1: Introduction to HIR v1.0
— Release of HIR version 1.0: How to Download and Use the Roadmap
— Presentations from HIR Technical Working Group chairs
Day 2: TWG Breakout Sessions for HIR v2.0 (TWG Caucus & Cross-TWG meetings)

Sponsors:

We thank our financial supporters for 2019:
 



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.

A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity, and assembled a group of leading technical experts to develop this Roadmap. The first work product of the Roadmap team is being presented by the chairs of the 20 Technical Working Groups. This Version 1.0 is now being released, for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, 21 February 2019: Introduction to HIR v1.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00: Start of Program: Welcome – Ajit Manocha, President & CEO, SEMI Int’l
9:15 – 10:50 AM – Session 1 – Heterogeneous Integration for High Performance
                Chair: Bill Bottoms, 3MTS
    — High Performance Computing & Data Center, Kanad Ghose (Binghamton U), Dale Becker (IBM)
    — 3D and Interconnect, Ravi Mahajan (Intel)
    — WLP (fan-in and fan-out), Rozalia Beica (DOW), John Hunt (ASE)
    — Thermal Management, Madhu Iyenger (Google), Azmat Malik
    — Integrated Photonics, Amr Helmy (U-Toronto), Bill Bottoms (3MTS)
    — Test, Dave Armstrong (Advantest)
BREAK
11:05 – 12:40 PM – Session 2 – Heterogeneous Integration for Consumer and Industrial Applications
                Chair: Subu Iyer, UCLA
    — Emerging Devices, Meyya Meyyappan (NASA Ames)
    — Medical, Health and Wearables, Mark Poliks (Binghamton U), Nancy Stoffel (GE)
    — SiP & Modules, Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon)
    — Single Chip and Multi Chip Packaging, William Chen (ASE), Annette Teng (Promex)
    — Integrated Power Packaging, Doug Hopkins (NCSU), Patrick McClusky (UMD)
    — IoT, Robert Lo (ITRI Taiwan)
12:40 – 1:40 PM – LUNCH     (discussions; box lunch included)
1:40 – 2:25 PM – PLENARY PRESENTATION
Invited Speaker: Babak Sabi, Corporate Vice President, General Manager of Assembly & Test Development, Intel Corporation
2:25 – 3:45 PM -Session 3 – Heterogeneous Integration for Special Applications
                Chair: Tom Salmon, SEMI
    — Aerospace and Defense, Tim Lee (Boeing)
    — 5G in RF and Analog Mixed Signal, Tim Lee (Boeing), Herbert Bennett (Alta Tech)
    — Cyber Security, Sohrab Aftabjahani (Intel)
    — Simulation, Chris Bailey, (U-Greenwich), Xuejun Fan (Lamar)
    — MEMS and Sensor Integration, Shafi Saiyed (ADI)
BREAK
4:00 – 5:20 PM – Session 4 – Heterogeneous Integration Applications, Materials & Simulation
                Chair: Amr Helmy, Univ of Toronto
    — Automotive, Urmi Ray (STATS ChipPAC), Rich Rice (ASE)
    — Mobile, William Chen (ASE)
    — Materials and Emerging Research Materials, Bill Bottoms (3MTS)
    — Supply Chain, Tom Salmon (SEMI)
5:15 PM – Information on Release of HIR version 1.0; Download & Roadmap Use
5:30 PM – Wrap-Up

Friday, 22 February 2019: TWG Breakout Sessions for HIR v2.0
Who should attend: All HIR Technical Working Group members and anyone interested in participating or learning more about the Heterogeneous Integration Roadmap and participating in interaction, collaboration and feedback.
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30: Registration and refreshments
9:00: Start of Breakout Sessions
HI for Market Applications
• Mobile
• IoT
• Medical, Health & Wearables
• Automotive
• High Performance Computing and Data Center
• Aerospace and Defense
Heterogeneous Integration Components
• Single-Chip and Multi-Chip Packaging (including Substrates)
• Integrated Photonics
• Integrated Power Electronics
• MEMS & Sensor Integration
• RF and Analog Mixed-Signal Design
Design
• Co-Design
• Simulation
Cross-cutting Topics
• Emerging Research Materials
• Emerging Research Devices
• Test
• Supply Chain
• Security
• Thermal
Integration Processes
• SiP and Module
• 2.5D and 3D
• WLP (fan in and fan out)
3:30 – 4:00 PM – Wrap-Up

System Assembly using a Microchip Printer 🗓 🗺

— chiplets, electrostatic assembly, sort, transport, roll-based, planarization, interconnect, HI …

Speaker: Eugene Chow, PARC
register
Meeting Date: Thursday, January 24, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1901eps.eventbrite.com
Summary: We aim to develop a system which can rapidly assemble small semiconductor chips (<1mm) into electronic systems. The process uses chips initially in solution, and then sorts, transports, and orients chips with directed electrostatic assembly with open- and closed-loop control. Assemblies are then transferred to final substrates with a stamp or continuous feed roll-based method, and then electrically interconnected. The current laboratory systems have handled small chips (10um-500um) and demonstrated fine registration (<1um and <1°). Ultimately, massively parallel automated microassembly, analogous to a xerographic printer using microchips instead of toner, could be used for integrating circuits, microLEDs and other semiconductor components into complex, heterogeneous systems.
Bio: Dr. Eugene Chow is a principal scientist and manager of the microsystems research group at PARC (a Xerox Company). The group works on novel printing-related processes, electronics and biomedicine. In the advanced electronics packaging area he focuses on lithographically defined microspring flip chip interconnects for integrated test, rework and packaging, and automated chiplet assembly. He leads research projects at PARC with support from Xerox, other companies and the government, and has ~100 patents granted/filed. He earned a B.S. from UC Berkeley in engineering physics, and did graduate work at Stanford University (MS engineering management, MS and PhD in electrical engineering).

TI Coordinates:
TI Conference Center, Santa Clara
37.375686
-121.999004

Holistic Design in Optical Interconnects 🗓 🗺

— high-performance, bandwidths, power budget, low-cost approaches, photonics co-design …

Speaker: Dr. Azita Emami, Professor, California Institute of Technology, and IEEE-SSCS Distinguished Lecturer
register
Meeting Date: Thursday, December 6, 2018
Time: 6:00 PM Networking and refreshments; 6:30 PM Presentation
Cost: Free, donation is accepted for refreshments: $2 IEEE members/$5 non-members, pay online or at the door

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-sscs/upcoming-events
Summary: The scalability of CMOS technology has driven computation into a diverse range of applications across the power-consumption, performance and size spectra. Today, Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large-scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular, effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.


Bio: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

Enabling System Performance through Practical Thermal Innovation

Speaker: (name, affiliation)
register
Presentation Slides: “title” (xx MB PDF) after meeting
Meeting Date: (day), January xx, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1901eps.eventbrite.com
Summary: There are tremendous challenges of increasing total power as well as high localized heat flux resulting from the growing push for heterogeneous integration on silicon and at the package level.
These challenges dictate that a thermal solution needs to be architected based on these factors: current density; power mapping; package structure; and assembly and reliability requirements.
This talk will explore the impact of selected thermal solutions at the packaging and assembly levels, as well as at the system level. It will emphasize how to co-design the thermal architecture with performance, reliability, mechanical and assembly requirements. We focus on having a full understanding of the end-user application. Also, this talk will disclose an innovative thermal solution that can extend the cooling limit by up to 50%.


Bio: Dr. Gamal Refai-Ahmed is a technical director at Xilinx, in San Jose. He is an ASME Life Fellow, a Fellow of the Canadian Academy of Engineering, and a Distinguished Engineer (and Adjunct Professor) at SUNY Binghamton. He obtained the M. A. SC. and Ph. D. degrees in Mechanical Engineering from the University of Waterloo. Gamal has made important contributions to electronics packaging and development of electronics cooling technologies for the consumer electronics, telecommunications and energy industries. He is the author of more than 90 technical papers and more than 100 US patents/International Patents/Pending patents.
Gamal is an Associate Editor of the IEEE/EPS Transactions on Components, Packaging and Manufacturing Technology, and the ASME Journal of Thermal Sciences and Engineering and Applications. He is the recipient of the 2008 Dxcellent Thermal Management award, 2010 Best Associate Editor J Electronics Packaging, 2010 Calvin Lecture and 2013 K16-Clock award in recognition for his scientific contributions and leadership in promoting best electronics packaging engineering practices. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation, the 2015 ASME service award and the 2016 IEEC SUNY-Binghamton Innovation leader of the year.

Improving the IEEE: Issues, Ideas, Best Practices 🗓 🗺

— listening session, better methods/tools, local needs, actionable, with Division Director …

[Whether or not you can attend, you can leave suggestions for improvements in the COMMENTS box below.]
Speaker: Dr. Renuka Jindal, Director, IEEE Division I; and Eminent Scientist and CTO, Vanderziel Institute of Science and Technology, LLC.
register
Meeting Date: Saturday, December 1, 2018
Time: 2:00 – 4:00 PM
Cost: none
Sponsors: SCV chapters of the CAS, EPS, SSCS, EDS, ComSoc, Nano (plus other) Societies/Councils

Location: Santa Clara University (Benson 21), Santa Clara (free parking in the SCU garage) – Click for full-size map
Reservations: 1812eps.eventbrite.com (no charge)
Summary: This will be an event “for listening to” engineers and managers in Silicon Valley who have ideas for improving the IEEE, or have issues they’d like to raise. With input and grass-roots suggestions for improving the IEEE, I intend to provide actionable feedback at the IEEE TAB and BOD level. Your input will be critical in shaping the future of the IEEE and will need your active support to make this a reality.
If you wish to bring specific thoughts about IEEE changes, improvements and growth, be prepared to present them to the group for, say, 5 minutes, for discussion and enhancement. The meeting secretary will take notes, along with any handouts you provide, and ask for others who would like to be further involved with your specific suggestion. Renuka will receive your inputs and the summary, and is taking steps to allow him to gather world-wide input on these specific ideas that can inform and support the issues that are raised by our SV community of entrepreneurs.


Bio: Dr. Renuka Jindal’s technical focus has been on research and teaching in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications and biological systems. He was with Bell Labs at Murray Hill, Princeton and Whippany, NJ as a distinguished member of technical staff for 22 years, bridging both technical and administrative roles. Highlights include his pioneering work in developing a physical understanding of noise in MOS devices with few hundred nanometers regime channel lengths and ultra-low noise amplification of fiber-optic signals. Until recently, he has served as Professor of Electrical and Computer Engineering, University of Louisiana at Lafayette.
As a 41 year veteran of IEEE with a dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS president in 2010-2011, and now serves as Director of IEEE Division I, sitting on the IEEE Board. As EDS president he formulated the vision and mission of EDS, enhancing member benefits and launching a plethora of initiatives reversing the decline in EDS membership. He brought together 6 societies and 1 council to launch the highly successful IEEE Journal of Photovoltaics, mushrooming IEEE’s share in the PV space. He Launched the EDS webinar series serving the practicing engineer, now considered a best practice in IEEE. And he Launched the 1st EDS OPEN ACCESS Journal J-EDS. He is also a recipient of the IEEE 3rd Millennium medal.

Please summarize your suggested changes/improvements in the COMMENTS box below, or email them to the Webmaster.

FPGA Heterogeneous Packaging Applications: Trends and Challenges 🗓 🗺

— HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution …

Co-sponsored by the Solid State Circuits Chapter
Speaker: Suresh Ramalingam, PhD., Fellow, Manager Advanced Packaging Interconnect Technology Development, Xilinx
register
Presentation Slides: “FPGA Heterogeneous Packaging Applications: Trends and Challenges” (1.6 MB PDF)
Meeting Date: Wednesday, November 14, 2018
Time: 11:30 AM Registration (and pizza/water); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1811eps.eventbrite.com

Summary: Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.

Bio: Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from the Massachusetts Institute of Technology. He holds 24 US Patents, the 2013 SEMI Award, the Ross Freeman Award for Technical Innovation, ECTC 2011’s Conference Best Paper Award, and IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D. He started his career at Intel developing Organic Flip Chip Technology for microprocessors which was implemented on Pentium I (Intel’s first flip chip product for laptops) in 1997. As one of the co-founders and Director of Packaging Materials at Scion Photonics, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D for Xilinx FPGA products.

The Road Ahead: Outlook for the Electronics Packaging Industry 🗓 🗺

— projections for AI, autonomous vehicles, crypto, OSATs, foundries, outlook …

Speaker: E. Jan Vardaman, President, TechSearch International, Inc.
register
Presentation Slides: “The Road Ahead: Outlook for the Industry” (2 MB PDF)
Meeting Date: Monday, October 22, 2018
Time: 12:30 PM Registration, lunch, and presentation (ending at 2:30 PM)
Cost: $25

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: fs24.formsite.com/meptec/form171
Summary: The semiconductor industry has seen record growth in the last few years, but with slowing growth in smartphone shipments and PC sales, what’s next? What will drive growth in advanced packaging? Is it Game Over for Cryptocurrency? Artificial Intelligence and automotive electronics are bright spots, but what types of packages will be used? How will OSATs benefit and what role will the foundry play? This presentation will examine economic and technology trends and provides an outlook for the industry.


Bio: Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia, and on the US mission to study manufacturing in China. She is a member of IEEE EPS, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE EPS Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.