Automotive Sensor Packaging Trends πŸ—“

— self-diagnostics, crash avoidance, driver assistance, image sensors, LiDAR, radar, challenges …

Speaker: Jan Vardaman, TechSearch Int’l.
Meeting Date: Wednesday, October 18, 2017
Time: 8:00 AM (PDT)
Cost: none; only open to EPS members

Location: on the Internet
Summary: An increasing number of sensors are used in automotive applications. Familiar sensors applications include air bags and tire pressure sensors. New automotive safety features include improved self-diagnostics, crash avoidance technology, and advanced driver assistance. This translates into increase use of image sensors, LiDAR, and radar. Multiple combinations of sensors are anticipated. What types of semiconductor packages are used in these automotive electronics and what are the future challenges as new package types are adopted? This presentation discusses some of the opportunities in automotive packaging and the challenges in meeting automotive specifications.

Bio: Jan Vadarman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE CPMT (now EPS) and is an IEEE CPMT (EPS) Distinguished Lecturer. She is a member of SEMI, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

3D Printing in Electronics Packaging: Hype, Hope, or Happening? πŸ—“

— design tools, materials, 3D-printing processes, micro-assembly systems, deposit, cure, embedded components …

Speakers: Dr. Chris Bailey, University of Greenwich, and Dr. Jie Xue, Cisco
Meeting Date: Tuesday September 19, 2017
Time: 8:00 AM (PDT)
Cost: none (for CPMT/EP members only)
Location: on the Internet
Summary: 3D-Printing (or Additive Manufacturing) has received significant media attention during the last five years. In 2012 the Economist published an article on this technology which stated that it will lead to a 3rd industrial revolution. A number of companies are now commercializing materials, design/software and 3D-Printers, and these are being used in a number of manufacturing sectors including aerospace, medical, and construction and consumer products. In China alone the 3D-Printer market is expected to be worth over 10Bn RMB by 2018, and the Government has recently initiated a policy to provide every school with 3D-printing capabilities.
But what impact will 3D-printing have on the electronics packaging and manufacturing community? Will 3D-Printing be just hype, or is there hope that these technologies will impact the way we manufacture and package electronic systems — or are developments already being commercialized? Will 3D-Printing of electronic circuits or components be the next phase of the additive manufacturing revolution? This presentation will discuss the challenges for design tools, materials, and 3D-printing processes in the context of electronics manufacturing/packaging. In particular, printing and micro-assembly systems are required that can accurately deposit and cure both functional and structural materials and place/embed components in an integrated manner within a single platform. The performance and electrical behavour of printed conductive materials is also a challenge as they must meet the performance of materials currently used. And of course the overall quality and reliability of 3D-printed electronic systems must meet industry requirements. This presentation will detail the current status of 3D-printing for the manufacture of electronic systems, and provide some insights on how it may impact our community in the future.

Bio: Dr. Jie Xue is currently the Sr. director of the Component Quality and Technology Group at Cisco Systems, Inc., San Jose. Her team is responsible for component technology development and qualification of ASIC, network processors and optical modules, as well as the development of advanced semiconductor and packaging technologies. Since joining Cisco in 2000, she has been working on developing high performance flip chip packaging, system-in-package, multi-chip modules, and chip-scale-packaging for high-reliability networking products. Prior to joining Cisco, Jie held several management and engineering positions in Motorola Inc., working on R&D and product development.
Bio: Dr. Chris Bailey is Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. He received his PhD in Computational Modeling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, he worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.

Probabilistic Design for Reliability in Electronics and Photonics πŸ—“

— accelerated testing, stressors, vulnerable elements, sensitivity analyses, predictive modeling, robustness, assured levels …

Speaker: Ephraim Suhir, Ph.D.
Webinar Date: Wednesday, July 19, 2017
Time: 8 AM PDT (11:00 AM EDT)
Cost: none (open only to CPMT members)
Location: on the Internet
Summary: The recently suggested probabilistic design for reliability (PDfR) concept in electronics and photonics (EP) is based on 1) highly focused and highly cost-effective failure-oriented accelerated testing (FOAT), aimed at understanding the physics of the anticipated failures, and at quantifying, on the probabilistic basis, the outcome of FOAT conducted for the most vulnerable element(s) of the product of interest for its most likely applications and the most meaningful combination of possible stressors (stimuli); 2) simple and physically meaningful predictive modeling (PM), both analytical and computer-aided, aimed at bridging the gap between the FOAT data and the most likely operation conditions; and 3) subsequent FOAT-and-PM-based sensitivity analyses (SA) using the methodologies and algorithms developed as by-products at the two previous steps. The PDfR concept proceeds from the recognition that nothing is perfect and that the difference between a highly reliable and an insufficiently reliable product is “merely” in the level of the probability of its failure. If this probability, evaluated for the anticipated loading conditions and the given time in operation, is not acceptable, SA can be effectively employed to determine what could/should be changed to improve the situation. The PDfR analysis enables one also to check if the product is not over-engineered, i.e., is not superfluously robust. If it is, it might be too costly. The operational reliability cannot be low, but it does not have to be higher than necessary either. It has to be adequate for the given product and application. When reliability and cost-effectiveness are imperative, ability to optimize reliability is a must, and no optimization is possible if reliability is not quantified. It is shown also that the optimization of the total cost associated with creating a product with an adequate (high enough) reliability and acceptable (low enough) cost can be interpreted in terms of the adequate level of the availability criterion. The major PDfR concepts are illustrated by practical examples. We elaborate on the roles and interaction of analytical (mathematical) and computer-aided (simulation) modeling. It is shown also how the recently suggested powerful and flexible Boltzmann-Arrhenius-Zhurkov (BAZ) model and particularly its multi-parametric extension could be successfully employed to predict, quantify and assure operational reliability. The model can be effectively used to analyze and design EP products with the predicted, quantified, assured, and, if appropriate and cost-effective, even maintained and specified probability of operational failure. It is concluded that these concepts and methodologies can be accepted as an effective means for the evaluation of the operational reliability of EP materials and products, and that the next generation of qualification testing (QT) specifications and practices for such products could be viewed and conducted as a quasi-FOAT that adequately replicates the initial non-destructive segment of the previously conducted comprehensive full-scale FOAT.

Bio: Ephraim Suhir is a reliability physics and materials science specialist in the area of electronics, opto-electronics and photonics engineering and applied science.

The Future of Additive Manufacturing of Radio-Frequency Components πŸ—“

— 3D printing, raw materials, deposition, effects on design, agile, state of practice …

Webinar Sponsor: Proceedings of the IEEE
Speakers: β€’ Roberto Sorrentino (University of Perugia, Italy); β€’ Petronilo Martin-Iglesias (European Space Agency, The Netherlands); β€’ Oscar Antonio Peverini (CNR – IEIIT, Italy); β€’ Thomas M. Weller (University of South Florida, USA)
Meeting Date: Thursday, May 18, 2017
Time: 8:000 AM (PDT)
Cost: none
Location: on the Internet
Summary: Additive manufacturing (AM), commonly referred to as 3D printing, is a booming technology (or, better, a set of technologies) in a number of application areas, including architecture, automotive, aerospace, biotech, electronics, fashion and food to name just a few. AM actually encompasses a broad array of processes aimed to directly synthesize a 3D object from raw materials, using a layer-by-layer deposition or growth sequence under computer control.
In the electronic market, and specifically in the RF and Microwave field, from expensive satellite communication systems to high volume microwave electronics, AM has the potential to change the way systems are designed, integrated and operated and is therefore considered a strategic technology and a key enabler for accelerated engineering processes, highly efficient products and new agile supply chains. Totally new design approaches that will improve performance, make mass optimization practical, allow the miniaturization of complex systems and dramatically reduce the design/manufacturing/assembly cycle costs are possible with AM. Along with these attributes AM provides an environmentally-friendly alternative to conventional manufacturing.
This webinar will present a review of the current state of practice in additive manufacturing for RF/microwave applications including those areas where much remains to be done.

How to Create Cooler Power Systems with Simulation Tools πŸ—“

β€” SPECTRUM Webinar – models, data sheets, calculations, analysis, options, examples …

Speaker: Mike DeGaetano, systems application engineer, Vicor
Webinar Date: Thursday, November 3, 2016
Time: 5:00 AM (PST)
Cost: none
Location: on the Internet
Summary: Good thermal design is essential if engineers are to achieve the power densities demanded by modern systems. This webinar explains how precise thermal calculations can be made using data sheets and application notes, allowing power developers to ensure they optimize the system’s cooling. It then addresses new simulation tools that allow preliminary feasibility studies to be conducted in just a few clicks, saving power designers valuable time. The webinar will address:
— Thermal models and the three main cooling methods
— Precise thermal calculation based on data sheets, application notes and safe operating areas
— Online simulation tools that take the pain out of thermal calculations
— How to use thermal simulators for quick analysis of different cooling options
— Worked examples of thermal calculations for real-world power systems

Bio: Mike DeGaetano is a systems application engineer at Vicor, providing applications support and design expertise for the integration of Vicor products. He has authored a number of application notes, and has a BSEE and MS in Electrical Engineering from the University of New Hampshire. Prior to his time at Vicor, he designed PCB test fixtures for processor interfaces.

CPMT Webinar: Manufacturing Micron-sized Systems πŸ—“

β€” mm-sized pills, functionality, manufacturability, new processes …

Speaker: Walt Trybula, Trybula Foundation, Inc. (Austin)
Meeting Date: Thursday, October 27, 2016
Cost: none (open only to CPMT members)
Location: on the Internet
Summary: Electronics is ubiquitous in today’s world. Semiconductors provide the computing power and data conversion. Power sources, typically batteries, on small, uncorded devices are challenging for long operation. Heat generation, i.e., power loss, is a significant concern. The packaging is designed to survive both the anticipated environmental extremes and the application handling. The system is held together via a substrate that connects the various elements of the application into a functional circuit. Millimeter sized “pills” with video capability have been designed and applied in medical applications. As the size of the β€œsystems” continues to shrink into the micron range, the question that arises is “How can we design a system that can perform its mission and still be manufactured in quantity?” This presentation addresses some of the potential issues that need to be resolved in order to be successful. One critical fact is that the manufacturing processes do not exist today. They need to be invented. The intent of this paper is to initiate dialogue and research/development to accomplish the manufacture of micron-sized systems.

Bio: Walt Trybula is an IEEE Fellow and a Senior Member of IMAPS, a member of SPIE, a member of the American Society of Information Science (ASIS), and a member of the Association Computing Machinery (ACM). He is an elected member of the Board of Governors for the IEEE/CPMT Society and is the current Editor-in-Chief and Founding Editor, IEEE Transactions on Electronics Packaging Manufacturing (previously titled: Manufacturing).
As a technology futurist, he has focused his current activities on evaluating emerging trends and applications in nanotechnology, mesomaterials, MEMS/NEMS, and semiconductors with an emphasis on feasibility evaluation and profitable business insertion. His most recent published material is on nanotechnology, cleaning/contamination issues, nano patterning, and cost effective application of technology. He is an IEEE Distinguished Lecturer.

8th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop πŸ—“ πŸ—Ί

β€” tutorials, alpha upset, materials selection, process control, case studies …

Date: Thursday, November 3, 2016
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Juniper Networks, Building 6, 1215 Borregas Ave, Sunnyvale
Attendance: On-site or Remote (WebEx)
Cost: Free
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Juniper Networks; Pure Technologies; Cisco Systems; XIA.

Our annual IEEE Soft Error Rate Workshop, now in its 8th year, focuses on alpha-induced soft errors with its unique offering of simultaneous on-site and remote participation. It provides opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
This year’s event has a new format: We will be inviting industry experts in the field to offer three tutorials on fundamentals of alpha-related soft errors (shown in red below), to bring engineers and managers up to speed, interspersed with three presentations on current issues, solutions and case studies. Note that all times are Pacific Standard Time; please convert, for your location.
For those participating via WebEx on the Internet, we will send log-in information to all registrants on Wednesday, November 2nd.
See summaries of the contents of the tutorials and talks at this location.


Time (PST) Presenter Title
9:30 AM Check-in and Registration
10:00 AM Eric Crabill, Xilinx Tutorial: An Introduction to Single Event Effects (more)
10:45 AM Adrian Evans, iROC Tutorial: System Design Considerations for Soft Error Mitigation (more)
11:30 AM Rick Wong, Cisco Challenges of Alpha Testing (more)
12:00 Noon Lunch and Exhibits
1:00 PM Brendan McNelly, XIA; Mike Gordon, IBM Tutorial: Techniques and Challenges of Alpha Emissivity Measurements (more)
1:45 PM Laura Monroe, Los Alamos National Lab Resilience and Inexact Computing (more)
2:15 PM Francis Classe, Cypress Soft Error Upset Sensitivity to the Array Background Pattern in SLC Floating Gate and Charge Trapping Flash Memories (more)
2:45 PM Eric Crabill, Xilinx Alpha-Induced Soft Errors in Xilinx UltraScale+ Devices – Not a ‘Material’ Issue (more)
3:30 PM Close of Workshop

Webinar: IoT is the Body, AI is the Brain πŸ—“

β€” from the IEEE’s IoT Committee: convergence, sentient environment, serendipity …

β€” from the IEEE’s IoT Committee: convergence, sentient environment, serendipity …
Speakers: Jay Iorio, Innovation Director; IEEE Standards Association; BC “Heavy” Biermann, educational technologist; Heather Schlegel, The Purple Tornado
Webinar Date: Wednesday, May 18, 2016
Time: 8:00 AM
Cost: none
Location: on the Internet
Reservations: not required
Summary: In a quickly unfolding near-future, the Internet of Things will merge with other technologies – e.g., mixed reality, data analytics – to create the beginnings of a sentient and interactive physical environment. The potential of this grand convergence will be enabled by what we today call artificial intelligence. But how will developers encode the human need for randomness and serendipity into the software that will make increasingly important and autonomous decisions in our lives?
Is an echo chamber, in which one experiences only what one wants to experience, an inevitable consequence of delegating control to ubiquitous intelligent systems? If IoT is the body and AI is the brain, where is the soul?

Speakers: Jay Iorio is the Innovation Director for the IEEE Standards Association. His primary focus is the emerging technologies of virtual worlds, augmented reality, and serious games. Iorio built and currently manages IEEE Island in Second Life and has worked extensively with advanced publishing technologies, multimedia, and 3D user interfaces. He is also a composer, machinimatographer, and creator of the Etherfilm studio complex in Second Life. He recently spoke on a panel at the South by Southwest (SXSW) Festival on augmented reality.
BC “Heavy” Biermann is an educational technologist, academic, and digital artist. BC has a PhD in Humanities (Intermedia Analysis) from the Universiteit van Amsterdam, and derives his alias from his love for philosophical discussion. With an interdisciplinary background that comprises technology, philosophy, and the arts, he has worked as both a university professor and a tech developer.
Heather Schlegel is a futurist. Most people know her by her apt moniker, heathervescent. She is a social scientist who studies future trends to help people understand and take advantage of change. Heather does this through speaking, consulting, research projects, design fictions and media productions. Her company, The Purple Tornado, has been around since 2006. Prior to the Purple Tornado, Heather helped build and launch more than 50 Internet products at over 30 startups from 1996 to the 2005 in Silicon Valley and Los Angeles. Recently, she completed an assignment with the Swift Innovation Team, Innotribe, based in New York, NY and La Hulpe, Brussels. She is best known for her research on the Future of Transactions, which she presented at SxSW, Sibos, TedxZwolle, The Future of Money, Tomorrow’s Transactions and other conferences around the world. Heather is the producer and creator of four short films, including “Fly Me to the Moon” nominated for Most Important Futures Award by the Association of Professional Futurists, 2012; “Flowers for Grandma;” “Innotribe Startup Challenge Documentary” and “Slices of Life.”