Integrated Power: A Virtual Panel Session 🗓

— miniaturized power supplies, Power Systems on Chip (PSoC), integrated magnetics, switched-capacitors, options …

Speakers: Steve Allen, pSemi; Kirk Bresniker, HP Labs; Wonyoung Kim, Lion Semi; Stephen Oliver, Navitas; Noah Sturcken, Ferric
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Meeting Date: Thursday, October 22, 2020
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 4:30 PM
Cost: none (on the Internet)
Reservations: ewh.ieee.org/r6/scv/pels/
Summary: Power Systems on Chip (PSoC) have evolved significantly over the past decade or two and have made inroads into mass production. Between integrated magnetics and switched-capacitor ICs, there are many options for integrated power available today. Solutions have been used in mass-market cell phones, telecommunications hardware and more.
Our speakers will discuss specific technologies they’ve developed to help miniaturize power supplies and push higher power density. We will then have a discussion comparing and contrasting the technologies, and field questions about how they can be used in applications. Each of five main panelists will provide a short position presentation, which will be followed by an interactive panel session and LIVE Q&A from the audience.

Ribbon Alumina Laminate for PCBs and Substrates 🗓

(Tim Orsley) — attributes, homogeneous, signal skew, loss tangent, stresses, drilling, process flow …

Speaker: Timothy Orsley, Senior Research Associate, Corning
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Meeting Date: Thursday, October 29, 2020
Time: Checkin via WebEx after 11:50 AM; Presentation at 12:00 noon (PDT)
Cost: none
Reservations: eps2010b.eventbrite.com
Summary: Because ceramic materials are inherently brittle, vias have traditionally been made in the green state prior to sintering. Since the sintering is done by the ceramics vendor (at very high temperature), the onus is upon them to fabricate the vias beforehand, thus making the material custom and costly. This stands in stark contrast to PCB materials which are generic when delivered, being customized instead by the purchaser. Corning’s new ribbon alumina laminate is the first ceramic product that allows for PCB processing — even mechanical drilling. The ribbon alumina essentially supplants the traditional glass weave and, being homogeneous, eliminates differential signal skew. The laminate supports very high speed signaling, such as 5G, with very low loss tangent and dielectric constant. Applicable both as PCB and package substrate: use in PCBs dramatically reduces overall CTE mismatch, while use as a package substrate better distributes stress. This presentation will consider the process flow of traditional ceramics in contrast with Corning’s new ribbon alumina laminate, and provides details on important laminate attributes.

Bio: Tim Orsley received degrees in electrical engineering and materials science from Stanford University, then worked locally at a number of Silicon Valley startups and companies. He retired from HP in 2001, then served as “Mr. IEEE” for the San Francisco Bay Area for 10 years. As vice president of publications for the Electronics Packaging Society for 22 years, he supervised four archival journals and a newsletter. He received the IEEE’s Centennial Medal, the Board’s Distinguished Service award, the Society Contribution Award, and the IEEE’s Third Millennium Medal. He is a Life Fellow of the IEEE, and has served as chapter treasurer and chair, and is currently chapter advisor.

Heterogeneous Integration for the Aerospace and Defense Sectors 🗓 🗺

(Jeff Demmin) — specific challenges, extreme performance, security, low volumes, roadmap …

Free IEEE-EPS Webinar
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Speaker: Jeffrey Demmin, Semiconductor and Defense Project Manager, Keysight Technologies
Meeting Date: Wednesday, October 21, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: on the Internet
Info and to Register: eps.ieee.org/education/eps-webinars.html
Summary: The Aerospace and Defense Chapter of the Heterogeneous Integration Roadmap addresses the specific challenges of A&D electronics, including long product lifecycles, low volumes, demanding environments, security, and extreme performance requirements. This webinar will review the landscape for A&D heterogeneous integration from the inaugural 2019 edition, as well as the high-level roadmap table being rolled out in the 2020 update.

Bio: Jeff Demmin is the Semiconductor and Defense Project Manager at Keysight Technologies in Santa Rosa, CA. Previously he was a Senior Lead Scientist at Booz Allen Hamilton, where he worked on heterogeneous integration programs for DARPA and other government clients. Before that, he was with STATS ChipPAC, and he worked for over a decade at Tessera in corporate development and IP acquisition. His career started in semiconductor package design at National Semiconductor, and he has also served as the Editor-in-Chief of Advanced Packaging magazine. He has a Bachelor’s degree in Physics from Princeton and a Master’s degree in Materials Science from Stanford. He has been in the industry long enough that all of his patents have expired.

Design And Materials Challenges For Cost-Effective High-Performance LEDs 🗓

(TY Hin) — solid state lighting, design, materials, processes, challenges, innovative approaches …

Speaker: Tze (TY) Hin, PhD, Director of Packaging, Technology Research & Development, LUMILEDS
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Meeting Date: Thursday, October 15, 2020
Time: 12:00 Noon (PDT)
Cost: none
Location: On the Internet (via WebEx)
Reservations: 2010eps.eventbrite.com
Summary: The rapid development of solid state lighting applications is driving the need for innovative approaches in LED packaging. While the majority of high-power emitters are still using conventional packaging methods, there are next-generation LED technologies and applications that requires integration of existing approaches with IC packaging knowhow. The LED industry is also driving low-cost solutions to the design, materials and processes in order to be market-competitive due to the emergence of LED suppliers in Asia, particularly in China. This talk will discuss the challenges in the LED integration structure from die to package, package to board and system, focusing in identifying challenges that need to be overcome in optical design, materials, and manufacturing processes. Comparison of similarities and opportunities in both LED and IC packaging will be discussed.

Bio: Tze Yang Hin has 20 years of packaging development experience. He is currently managing LED packaging development activities atLUMILEDS. He has authored and co-authored over 20 technical papers and patent filings in the area of electronics packaging. His current research interest is next-generation mini/micro LED packaging and low-cost packaging innovation.

Packaging of Electronics for Medical, Health and Wearables Applications 🗓

— heterogeneous integration, advance packaging, new materials, assembly technologies, forecasts …

Free IEEE-EPS Webinar
Speaker: Dr. Mark D. Poliks, Binghamton University
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Meeting Date: Thursday, September 10, 2020 (view the on-demand webinar)
Time: 8:00 AM (PDT)
Cost: none
Location: on the Internet
Access Webinar: eps.ieee.org/education/eps-webinar-archive.html
Summary: There is increasing interest in wireless medical and health monitoring. The adoption and continued innovation in flexible hybrid electronics is expected to drive this industry in the years to come — greater functionality in thinner and smaller spaces for both medical-grade and consumer-grade-based health monitors, as well as implantable and other medical devices. While traditional medical electronics may remain conservative in design, the adoption of flexible hybrid electronics for wearables that significantly advance packaging and assembly technologies are in the early stages. The integration of a variety of components and die (including thinned and unpackaged processors, memory, sensors, MEMS, RF, optical, power sources, etc.), together with printed circuits on thin flexible substrates, will create the next generation of wearable medical systems. Many new materials, assembly methods and applications are now demonstrated in the literature.
This presentation will describe these technologies including the target applications, the materials, deposition methods, components, device integration and reliability. It will discuss trends and challenges expected in the coming years.

Bio: Mark Poliks is a Professor of Materials Science and Engineering and Director of the Center for Advanced Microelectronics Manufacturing at Binghamton University. In 2006 he established the first research center to explore the application of roll-to-roll processing methods, including large-area photolithography, to flexible electronics and displays, with equipment funding from the United States Display Consortium (USDC) and the Army Research Lab. His research is in the areas of industry relevant topics that include: high performance electronics packaging, flexible hybrid electronics, medical and industrial sensors, materials, processing, aerosol jet printing, roll-to-roll manufacturing, in-line quality control and reliability. H He is the recipient of the SUNY Chancellor’s Award for Excellence in Research. He leads the New York State Node of the DoD NextFlex Manufacturing USA and was named a 2017 NextFlex Fellow. He has authored more than one-hundred technical papers and holds forty-eight US patents. Previously he held senior technical management positions at IBM Microelectronics and Endicott Interconnect. He is an active member of the IEEE Electronics Packaging Society’s Electronic Component and Technology Conference and served as the 69th ECTC General Chair.

Design for Reliability and Accelerated Testing in Electronics and Photonics Packaging Engineering 🗓

— improved reliability, critical applications, product lifetime, DfR, HALT …

Free IEEE-EPS Webinar
Speaker: Dr. Ephraim Suhir, Portland State University; Life Fellow of the IEEE; EPS Distinguished Lecturer
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Meeting Date: Tuesday, August 25, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: on the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: This webinar addresses an evolving philosophy of accelerated testing in electronic and photonic packaging, and could be viewed as a possible extension and modification of Highly Accelerated Life Testing (HALT) for applications where a high level of operational reliability is critical, such as aerospace, military, long-haul communications, self-driving vehicles, or medical. The highly focused and highly cost-effective Failure Oriented Accelerated Testing (FOAT) approach is suggested as a suitable experimental basis for the Probabilistic Design for Reliability (PDfR) concept. The PDfR concept is used to assess a product’s lifetime and the corresponding never-zero probability of failure in the field for the given product and application and make this probability adequate for the given product and application. The general concepts are illustrated by numerical examples.

Bio: Dr. Ephraim Suhir is a member of the Santa Clara Valley Chapter of EPS. He is on the faculty of Portland State University, USA; Technical University, Vienna, Austria; and James Cook University, Australia. He is also a Life Fellow of the IEEE, the American Society of Mechanical Engineers (ASME), the Society of Optical Engineers (SPIE), and the International Microelectronics and Packaging Society (IMAPS) and has over 400+ publications in electronics and reliability engineering. Ephraim is an EPS Distinguished Lecturer.

Integrated Photonics for Heterogeneous Integration 🗓

— design, analysis, current capabilities, challenges …

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Speakers: Bill Bottoms, 3MTS, and Amr Helmy, University of Toronto
Webinar Date: Thursday, August 6, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: On the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: This talk addresses photonics issues covered in the new IEEE Roadmap pertinent to high-performance computing, optical interconnects for electronic chips as well as data center applications. For example, power consumption and thermal management challenges are highlighted as key challenges to be addressed in the near future. The introduction of photonics into the transmission, processing and even the generation of data through optical-based sensors is a key enabling factor for continued progress in these areas as we reach the limits of physics, and the benefits of Moore’s Law scaling slow. Wherever possible, industry must adopt and adapt the packaging technologies developed for electronics to decrease cost and time-to-market for packaging of individual photonic ICs and incorporating them and other photonic components into the complex 3D Systems-in-Packages through heterogeneous integration.
Download Chapter 9, Integrated Photonics Packaging for pre-Webinar study.
Bill Bottoms Bio: Dr. Bill Bottoms received his Ph.D. from Tulane University and joined the faculty at Princeton Unviersity after graduation. He has worked in venture capital and was involved in founding several Companies including Tessera and Microwlectronics Packaging. He has served as Chairman and CEO of several companies both public and private. He currently serves as Emeritus member of the Board of Tulane University; Chairman of the SEMI Awards Committee; Chairman of Fluence Analytics; Member of the Board of MIT’s Microelectronics Center; Chairman of 3MTS; and Co-Chair of the Heterogeneous Integration Roadmap.
Bio: Amr Helmy is a Professor of Photonics at the University of Toronto, Canada. He received his Ph.D. from the University of Glasgow. After, he joined Agilent labs in the UK working for the semiconductor product group. He now leads a group in Photonics at the University of Toronto. He represents the IEEE Photonics Society within the IEEE Quantum Initiative and is Co-Chair of the HIR, also representing the Photonics Society.

Co-Design for Heterogeneous Integration 🗓

— electrical, thermal, mechanical, chip-package-board, design flow, new tools …

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Speakers: Prof. José Schutt-Ainé, UI-UC, and Prof. Rohit Sharma, Indian Institute of Technology Ropar
Webinar Date: Thursday, July 23, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: On the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: This talk focuses on current state-of-the-art, challenges and potential solutions for Co-Design. Electrical, thermal, and mechanical interactions across the chip-package-board domains can no longer be ignored. New modelling and simulation tools must accurately predict the physical (e.g. electro-thermal, thermo-mechanical, etc) coupling between multiple semiconductor components and the package/system that contains them. The Co-Design Chapter of the Heterogenous Integration Roadmap explores how design and analysis practices need to be defined in the context of heterogeneous integration. It addresses the traditional chip-package-board design flow as well as current capabilities and future challenges. The vision is to create an environment where design closure is achieved with a minimum number of iterations meeting all requirements for performance and cost. This environment must leverage from currently available technologies, namely computing power, algorithms and artificial intelligence.
Download Chapter 13, Co-Design for Heterogeneous Integration for pre-Webinar study.
José Schutt-Ainé Bio: José Schutt-Ainé received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), Urbana, in 1984 and 1988, respectively. In 1989, he joined the Electrical and Computer Engineering Department as a member of the Electromagnetics and Coordinated Science Laboratories, where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. He is a consultant for several corporations. His current research interests include the study of signal integrity and the generation of computer-aided design tools for high-speed digital systems. He is an IEEE Fellow and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018.
Rohit Sharma Bio: Rohit Sharma received the B.E. degree in electronics and telecommunication engineering from North Maharashtra University, India, in 2000, the M. Tech. degree in systems engineering from Dayalbagh Educational Institutes, India, in 2003 and the Ph.D. degree in electronics and communication engineering from Jaypee University of Information Technology, India, in 2009. He worked as a Post-Doctoral Fellow at the Design Automation Lab at Seoul National University, Seoul, Korea from Jan 2010 to Dec 2010. He was a Post-Doctoral Fellow at the Interconnect Focus Centre at Georgia Institute of Technology, Atlanta, USA from Jan 2011 to Jun 2012. Dr. Sharma joined the department of electrical engineering at the Indian Institute of Technology Ropar in 2012, where he is currently an Associate Professor. All along his tenure at IIT Ropar, he has initiated activities in the area of Electronic Packaging. His current research interests include design of high-speed chip-chip and on-chip interconnects, Graphene based nanoelectronic devices and interconnects, Signal and Thermal integrity in high-speed interconnects and 3D ICs/packages and application of Machine Learning in advanced packaging and systems. He is also the coordinator of the Indo-Taiwan Joint Research Centre on Artificial Intelligence and Machine Learning at IIT Ropar. He is an Associate Editor of the IEEE Transactions on Components, Packaging and Manufacturing Technology and a Program Committee member in IEEE EPEPS and IEEE EDAPS. He has been the General Co-Chair of the IEEE EDAPS in 2018. He is the Co-Chair of the IEEE EPS Technical Committee on Electrical Design, Modeling, and Simulation and is a Senior Member of the IEEE.

Test Technology for Heterogeneous Integration 🗓

— test cost, complexity, density, integration, performance, challenges …

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Speakers: Dave Armstrong, Director of Business Development, Advantest; Ken Lanier (Teradyne), Don Blair (Advantest) and Marc Hutner (Teradyne)
Webinar Date: Thursday, July 2, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: On the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: The Test Technology chapter of the new Roadmap highlights the challenges and opportunities for the semiconductor industry as we move forward. The chapter itself is divided into 15 different white papers because of the significant diversity of different challenges the test industry must face. Whether it’s a single cellphone SIP with incredible complexity or a use-once medical sensor where incredible accuracy is life-critical, the test industry must meet the needs. Dave Armstrong will deliver an overview, he will give brief updates on testing of photonic, memory, 2.5D, and specialty device testing. He will also discuss how system level test is improving test coverage at a reduced cost. Following will be updates on three of the fastest-changing areas of test.
With the significant recent increases in internet traffic, efficient testing of big-digital AI, server, and communications devices is more critical than ever before. Marc Hutner will discuss how logic test is confronting this challenge, including a discussion on how design-for-test (DFT) is both challenging and helping the industry as we move forward.
The roll out of 5G mobile phone devices is anticipated to be a world-changing advancement. Meeting this need requires many advances in the test technology of RF devices. Don Blair will provide an overview of how the test industry is changing in order to meet these challenges.
It is really difficult for the industry to maintain a cost-effective test cost when device complexity is growing in so rapidly and in so many directions. This makes it difficult to keep the cost-of-test from skyrocketing. Ken Lanier will discuss steps the industry is taking to meet these challenges and what the results and forecast is for device test costs.
Download Chapter 17, Test Technology for pre-Webinar study.

Bio: Dave Armstrong, in his capacity as Director of Business Development, works directly with customers and Advantest’s global R&D teams to define, develop and deliver creative solutions to the most demanding test challenges. Additionally, Dave is currently the Chairman of the Test Technology Working group for the Heterogeneous Integration Roadmap. Prior to joining Advantest in 2004, Dave spent over two decades in HP/Agilent’s IC test group achieving the role of Principal Engineer. Prior to joining HP Dave worked in the semiconductor industry in areas of IC and system design, product/yield engineering, as well as test engineering. Dave Armstrong received degrees in Electrical, Computer, and Environmental Engineering from the University of Michigan in 1974.


Ken Lanier is Co Chair of the HIR Test Technology Working Group.


Don Blair is a Business Development Manager working for Advantest for 33 years (HP > Agilent > Verigy > Advantest) and 5 years for Schlumberger before that. His experience base has been digital and mixed-signal testing starting with Series 10/20 and 80 and continuing on with the V93000 platform. He currently is the lead on the HIR TWG for the Analog Mixed Signal and RF teams.


Marc Hutner is the DfX Systems Engineering responsible for design to test solutions that accelerate ATE debug. He has worked at Teradyne for 20 years in a variety of engineering and technical management positions. This includes analog IP design, ASIC development management, Instrument design, ATE system definition and technical product management. He also is a contributor to the Heterogeneous Integration Roadmap for Semiconductors (formerly the ITRS roadmap) for test.

Modeling and Simulation for Heterogeneous Integration 🗓

— enabling technologies, tools, chip-package-board-system domains, challenges …

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Speaker: Prof. Chris Bailey, University of Greenwich
Webinar Date: Wednesday, July 8, 2020
Time: 8:00 AM (PDT)
Cost: none
Location: On the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: The Modeling and Simulation chapter of the Heterogeneous Integration Roadmap presents the clear need for modeling & simulation to support co-design across the die-package-board-system domains. At present electrical, thermal, and mechanical analysis is mainly undertaken separately, with electrical and recently thermal analysis undertaken for chip-design, and electrical, thermal, and mechanical analysis undertaken at the package/board and system levels by different design teams, generally using different tools. The future is a more integrated and collaborative approach, using multi-physics and machine learning tools, to address issues such as signal/power integrity, thermal management, and reliability. This webinar will detail the current state-of-the-art, challenges (such as chip-package interactions), and potential solutions to these. Several examples will be demonstrated detailing progress in modeling, simulation and characterization methodologies for multi-physics and multi-scale analysis.

Download Chapter 14, Modeling and Simulation for pre-Webinar study.


Bio: Chris Bailey is President of the IEEE Electronics Packaging Society and Director of the Computational Mechanics and Reliability Group at the University of Greenwich, UK. He has a PhD in Computational Modeling and an MBA in Technology Management and has published over 300 papers on the Design and Simulation of Electronics Packaging. Chris has served on several government committees, which includes the 2014 UK Research Excellence Framework, to assess research outputs and research impact across UK universities. He is a member of the EPSRC College (UK Equivalent to the NSF in the USA); and associate editor for the IEEE Transactions of Components, Packaging, and Manufacturing Technology. He is also the chair for the modeling and simulation technical working group on the Heterogeneous Integration Roadmap.
Bio: Xuejun Fan is a Regents’ Professor of Texas State University System, and Professor at Lamar University, Beaumont, Texas. He is an IEEE Fellow, and an IEEE Distinguished Lecturer. He currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors. He gained significant experience in the microelectronics industry between 1997 and 2007 at IME, Philips and Intel. He received the Outstanding Sustained Technical Contribution Award in 2017, and Exceptional Technical Achievement Award in 2011, from the IEEE Electronic Packaging Society. He is also co-chair for the modeling and simulation technical working group of the Heterogeneous Integration Roadmap.