A Moore’s Law for Packaging 🗓

— webinar: silicon scaling, imbalance with packaging, interconnect densities, new substrates, AI, medical applications …

Speaker: Subramanian S. Iyer, Electrical Engineering Department, UCLA, and Director of the Center for Heterogeneous Integration and Performance Scaling; past IBM Fellow
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Meeting Date: Wednesday, March 21, 2018
Time: 8:00 AM (PT)
Cost: none (only open to EPS members)
Location: on the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: While Silicon has scaled aggressively by over a factor of a few thousand over the last six decades the progress in packaging has been more modest — a linear factor 4-5 in most cases. In this talk, we will examine the reasons for this lag and what we are doing to fix this imbalance. Packaging is undergoing a renaissance where chip-to-chip interconnects can approach the densities of on-chip interconnects. We will discuss the technologies that are making this happen and how these can change our thinking on architecture and future manufacturing. Specifically, we will discuss two embodiments: Silicon as the next generation packaging substrate, and flexible electronics using fan-out wafer level processing. Finally, we’ll discuss how these developments can help put some intelligence into Artificial Intelligence and bring about changes in Medical Engineering.


Bio: Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. He was a Master Inventor at IBM. His current technical interests and work lie in the area of advanced packaging constructs for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as it treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.

Multi-Die Heterogeneous Integration: Design Considerations and Technology Demonstrations 🗓

— Webinar – multi-die integration, 2.5D and 3D, Heterogeneous Interconnect Stitching Technology, monolithic-like performance …

Speaker: Prof. Muhannad S. Bakir, ECE, Georgia Tech
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Webinar Date: Wednesday, January 31, 2018
Time: 8:00 AM (PT)
Cost: none (only open to EPS members)
Location: On the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: This presentation will discuss high-density multi-die integration approaches both in 2.5D and 3D, though we will emphasize 2.5D architectures. Specifically, we first discuss various 2.5D approaching including Heterogeneous Interconnect Stitching Technology (HIST), which enables the interconnection of multiple dice of various functionalities in a manner that mimics monolithic-like performance, yet utilizes advanced off-chip interconnects and packaging to provide flexibility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. A key feature of HIST is the ability to place a ‘stitch chip’ between adjacent ICs on the surface of an organic/ceramic package and use multi-height I/Os to interface the active dice to the package and stitch chips simultaneously. Design considerations and benchmarking (power delivery, signaling, and thermal) will be described and experimental demonstrations will be shown. Secondly, we discuss highly-scaled 3D ICs using sub-micron TSVs and report fabrication and characterization results; we also discuss the impact of TSV geometry on 3D end-to-end interconnect links (energy and latency) accounting on-chip wire resistance and capacitance. Third, and lastly, we briefly discuss 3D IC applications in CMOS multimodal biosensors.

Bio: Muhannad S. Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir and his research group have received more than twenty five conference and student paper awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded the 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology in the area of advanced packaging.
Dr. Bakir is Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology, Manufacturing Section and Editor of IEEE Transactions on Electron Devices.

The Origins of Silicon Valley: Early Technology and EPS Pioneers 🗓

— ham radio, early angel investors, patent issues, the klystron, innovation spirit, Stanford, Bud Eldon, new IRE Group, analog, digital, autonomous vehicles …

Speaker: Paul Wesling, H-P (retired), EPS VP-Publications (emeritus)
Moderator: Ken Pyle, co-founder of Viodi, LLC and Managing Editor of the Viodi View
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Presentation Slides: “The Origins of Silicon Valley: Early Technology and EPS Pioneers” (6 MB PDF) prior to webinar
Meeting Date: Monday, December 4, 2017
Time: 7:45 AM checkin; 8:00 AM presentation; 8:50 AM Q&A; 9:00 AM closing.
Cost: none (limited to current CPMT/EPS members)

Location: on the Internet (using WebEx)
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: Why did Silicon Valley come into being? The story goes back to the local hobby group of Hams (amateur radio operators) trying to break RCA’s tube patents, early Stanford engineers, the sinking of the Titanic and WW I, early “angel” investments, Fred Terman and Stanford University, local invention of high-power tubes (gammatron, klystron), WW II and radar, William Shockley’s mother living in Palo Alto, new approaches to running companies, and the SF Bay Area infrastructure that developed — these factors pretty much determined that the semiconductor and IC industries would be located in the Santa Clara Valley of California, and it would become the model for innovation worldwide. And since semiconductor device development and production were centered here, it made sense that Charles “Bud” Eldon of H-P would be asked by his management to start an IRE Group on Product Engineering in Palo Alto, to serve our local engineers (which grew into today’s EPS Society). Bud went on to become president of the IEEE.
Discover the exciting and colorful history of technology development and innovation that began in Palo Alto CA in 1910 and spread across the Santa Clara Valley. You’ll meet some of the colorful characters – Cyril Elwell, Lee De Forest, Bill Eitel, Charles Litton, Fred Terman, David Packard and others – who set leadership patterns for the electronics industries through their inventions and process development. You’ll find out about Charles “Bud” Eldon of HP, who founded a predecessor IRE Group in 1954 that become CPMT, now EPS, and served as president of the IEEE. Find out why Silicon Valley has had such an effect on the world.


Bio: Paul Wesling got interested in technology as a youngster. He went on to receive his BS in electrical engineering and his MS in materials science from Stanford University. Following assignments at GTE/Lenkurt Electric, ISS/Sperry-Univac, Datapoint Peripheral Products (VP – Product Integrity), and Amdahl (mainframe testing), he joined Tandem Computers in Cupertino (now part of Hewlett Packard) in 1985. He designed several multi-chip module prototypes, managed Tandem’s Distinguished Lectures series, and organized a number of advanced technology courses for his Division and also for the IEEE. He managed a grant from the National Science Foundation for the development of multimedia educational modules. Paul retired from HP in 2001, and then served for 10 years as the Communications Director for the IEEE’s S.F. Bay Area Council.

As Vice President of Publications from 1985 through 2008, he supervised four archival journals and a newsletter for IEEE’s Electronics Packaging Society. In this assignment he generated over $4 million in incremental revenue, for new Society programs and reserves. He is a Fellow of the IEEE, and received the IEEE Centennial Medal, the Board’s Distinguished Service award, the Society Contribution Award, and the IEEE’s Third Millennium Medal. He has organized over 500 courses for the local IEEE chapter in the Santa Clara Valley (Silicon Valley), many of them held at Stanford University (and, more recently, at Silicon Valley company facilities).

Automotive Sensor Packaging Trends 🗓

— self-diagnostics, crash avoidance, driver assistance, image sensors, LiDAR, radar, challenges …

Speaker: Jan Vardaman, TechSearch Int’l.
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Meeting Date: Wednesday, October 18, 2017
Time: 8:00 AM (PDT)
Cost: none; only open to EPS members

Location: on the Internet
Reservations: eps.ieee.org/education/eps-webinars.html
Summary: An increasing number of sensors are used in automotive applications. Familiar sensors applications include air bags and tire pressure sensors. New automotive safety features include improved self-diagnostics, crash avoidance technology, and advanced driver assistance. This translates into increase use of image sensors, LiDAR, and radar. Multiple combinations of sensors are anticipated. What types of semiconductor packages are used in these automotive electronics and what are the future challenges as new package types are adopted? This presentation discusses some of the opportunities in automotive packaging and the challenges in meeting automotive specifications.


Bio: Jan Vadarman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE CPMT (now EPS) and is an IEEE CPMT (EPS) Distinguished Lecturer. She is a member of SEMI, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

3D Printing in Electronics Packaging: Hype, Hope, or Happening? 🗓

— design tools, materials, 3D-printing processes, micro-assembly systems, deposit, cure, embedded components …

Speakers: Dr. Chris Bailey, University of Greenwich, and Dr. Jie Xue, Cisco
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Meeting Date: Tuesday September 19, 2017
Time: 8:00 AM (PDT)
Cost: none (for CPMT/EP members only)
Location: on the Internet
Registration: eps.ieee.org/education/ep-webinars.html
Summary: 3D-Printing (or Additive Manufacturing) has received significant media attention during the last five years. In 2012 the Economist published an article on this technology which stated that it will lead to a 3rd industrial revolution. A number of companies are now commercializing materials, design/software and 3D-Printers, and these are being used in a number of manufacturing sectors including aerospace, medical, and construction and consumer products. In China alone the 3D-Printer market is expected to be worth over 10Bn RMB by 2018, and the Government has recently initiated a policy to provide every school with 3D-printing capabilities.
But what impact will 3D-printing have on the electronics packaging and manufacturing community? Will 3D-Printing be just hype, or is there hope that these technologies will impact the way we manufacture and package electronic systems — or are developments already being commercialized? Will 3D-Printing of electronic circuits or components be the next phase of the additive manufacturing revolution? This presentation will discuss the challenges for design tools, materials, and 3D-printing processes in the context of electronics manufacturing/packaging. In particular, printing and micro-assembly systems are required that can accurately deposit and cure both functional and structural materials and place/embed components in an integrated manner within a single platform. The performance and electrical behavour of printed conductive materials is also a challenge as they must meet the performance of materials currently used. And of course the overall quality and reliability of 3D-printed electronic systems must meet industry requirements. This presentation will detail the current status of 3D-printing for the manufacture of electronic systems, and provide some insights on how it may impact our community in the future.

Bio: Dr. Jie Xue is currently the Sr. director of the Component Quality and Technology Group at Cisco Systems, Inc., San Jose. Her team is responsible for component technology development and qualification of ASIC, network processors and optical modules, as well as the development of advanced semiconductor and packaging technologies. Since joining Cisco in 2000, she has been working on developing high performance flip chip packaging, system-in-package, multi-chip modules, and chip-scale-packaging for high-reliability networking products. Prior to joining Cisco, Jie held several management and engineering positions in Motorola Inc., working on R&D and product development.
Bio: Dr. Chris Bailey is Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. He received his PhD in Computational Modeling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, he worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.

Probabilistic Design for Reliability in Electronics and Photonics 🗓

— accelerated testing, stressors, vulnerable elements, sensitivity analyses, predictive modeling, robustness, assured levels …

Speaker: Ephraim Suhir, Ph.D.
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Webinar Date: Wednesday, July 19, 2017
Time: 8 AM PDT (11:00 AM EDT)
Cost: none (open only to CPMT members)
Location: on the Internet
Reservations: cpmt.ieee.org/members-only.html
Summary: The recently suggested probabilistic design for reliability (PDfR) concept in electronics and photonics (EP) is based on 1) highly focused and highly cost-effective failure-oriented accelerated testing (FOAT), aimed at understanding the physics of the anticipated failures, and at quantifying, on the probabilistic basis, the outcome of FOAT conducted for the most vulnerable element(s) of the product of interest for its most likely applications and the most meaningful combination of possible stressors (stimuli); 2) simple and physically meaningful predictive modeling (PM), both analytical and computer-aided, aimed at bridging the gap between the FOAT data and the most likely operation conditions; and 3) subsequent FOAT-and-PM-based sensitivity analyses (SA) using the methodologies and algorithms developed as by-products at the two previous steps. The PDfR concept proceeds from the recognition that nothing is perfect and that the difference between a highly reliable and an insufficiently reliable product is “merely” in the level of the probability of its failure. If this probability, evaluated for the anticipated loading conditions and the given time in operation, is not acceptable, SA can be effectively employed to determine what could/should be changed to improve the situation. The PDfR analysis enables one also to check if the product is not over-engineered, i.e., is not superfluously robust. If it is, it might be too costly. The operational reliability cannot be low, but it does not have to be higher than necessary either. It has to be adequate for the given product and application. When reliability and cost-effectiveness are imperative, ability to optimize reliability is a must, and no optimization is possible if reliability is not quantified. It is shown also that the optimization of the total cost associated with creating a product with an adequate (high enough) reliability and acceptable (low enough) cost can be interpreted in terms of the adequate level of the availability criterion. The major PDfR concepts are illustrated by practical examples. We elaborate on the roles and interaction of analytical (mathematical) and computer-aided (simulation) modeling. It is shown also how the recently suggested powerful and flexible Boltzmann-Arrhenius-Zhurkov (BAZ) model and particularly its multi-parametric extension could be successfully employed to predict, quantify and assure operational reliability. The model can be effectively used to analyze and design EP products with the predicted, quantified, assured, and, if appropriate and cost-effective, even maintained and specified probability of operational failure. It is concluded that these concepts and methodologies can be accepted as an effective means for the evaluation of the operational reliability of EP materials and products, and that the next generation of qualification testing (QT) specifications and practices for such products could be viewed and conducted as a quasi-FOAT that adequately replicates the initial non-destructive segment of the previously conducted comprehensive full-scale FOAT.

Bio: Ephraim Suhir is a reliability physics and materials science specialist in the area of electronics, opto-electronics and photonics engineering and applied science.

The Future of Additive Manufacturing of Radio-Frequency Components 🗓

— 3D printing, raw materials, deposition, effects on design, agile, state of practice …

Webinar Sponsor: Proceedings of the IEEE
Speakers: • Roberto Sorrentino (University of Perugia, Italy); • Petronilo Martin-Iglesias (European Space Agency, The Netherlands); • Oscar Antonio Peverini (CNR – IEIIT, Italy); • Thomas M. Weller (University of South Florida, USA)
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Meeting Date: Thursday, May 18, 2017
Time: 8:000 AM (PDT)
Cost: none
Location: on the Internet
Reservations: bit.ly/2pwEhVK
Summary: Additive manufacturing (AM), commonly referred to as 3D printing, is a booming technology (or, better, a set of technologies) in a number of application areas, including architecture, automotive, aerospace, biotech, electronics, fashion and food to name just a few. AM actually encompasses a broad array of processes aimed to directly synthesize a 3D object from raw materials, using a layer-by-layer deposition or growth sequence under computer control.
In the electronic market, and specifically in the RF and Microwave field, from expensive satellite communication systems to high volume microwave electronics, AM has the potential to change the way systems are designed, integrated and operated and is therefore considered a strategic technology and a key enabler for accelerated engineering processes, highly efficient products and new agile supply chains. Totally new design approaches that will improve performance, make mass optimization practical, allow the miniaturization of complex systems and dramatically reduce the design/manufacturing/assembly cycle costs are possible with AM. Along with these attributes AM provides an environmentally-friendly alternative to conventional manufacturing.
This webinar will present a review of the current state of practice in additive manufacturing for RF/microwave applications including those areas where much remains to be done.

How to Create Cooler Power Systems with Simulation Tools 🗓

— SPECTRUM Webinar – models, data sheets, calculations, analysis, options, examples …

Speaker: Mike DeGaetano, systems application engineer, Vicor
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Webinar Date: Thursday, November 3, 2016
Time: 5:00 AM (PST)
Cost: none
Location: on the Internet
Reservations: spectrum.ieee.org/webinars
Summary: Good thermal design is essential if engineers are to achieve the power densities demanded by modern systems. This webinar explains how precise thermal calculations can be made using data sheets and application notes, allowing power developers to ensure they optimize the system’s cooling. It then addresses new simulation tools that allow preliminary feasibility studies to be conducted in just a few clicks, saving power designers valuable time. The webinar will address:
— Thermal models and the three main cooling methods
— Precise thermal calculation based on data sheets, application notes and safe operating areas
— Online simulation tools that take the pain out of thermal calculations
— How to use thermal simulators for quick analysis of different cooling options
— Worked examples of thermal calculations for real-world power systems

Bio: Mike DeGaetano is a systems application engineer at Vicor, providing applications support and design expertise for the integration of Vicor products. He has authored a number of application notes, and has a BSEE and MS in Electrical Engineering from the University of New Hampshire. Prior to his time at Vicor, he designed PCB test fixtures for processor interfaces.

CPMT Webinar: Manufacturing Micron-sized Systems 🗓

— mm-sized pills, functionality, manufacturability, new processes …

Speaker: Walt Trybula, Trybula Foundation, Inc. (Austin)
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Meeting Date: Thursday, October 27, 2016
Cost: none (open only to CPMT members)
Location: on the Internet
Reservations: cpmt.ieee.org/technology/cpmt-webinars.html
Summary: Electronics is ubiquitous in today’s world. Semiconductors provide the computing power and data conversion. Power sources, typically batteries, on small, uncorded devices are challenging for long operation. Heat generation, i.e., power loss, is a significant concern. The packaging is designed to survive both the anticipated environmental extremes and the application handling. The system is held together via a substrate that connects the various elements of the application into a functional circuit. Millimeter sized “pills” with video capability have been designed and applied in medical applications. As the size of the “systems” continues to shrink into the micron range, the question that arises is “How can we design a system that can perform its mission and still be manufactured in quantity?” This presentation addresses some of the potential issues that need to be resolved in order to be successful. One critical fact is that the manufacturing processes do not exist today. They need to be invented. The intent of this paper is to initiate dialogue and research/development to accomplish the manufacture of micron-sized systems.


Bio: Walt Trybula is an IEEE Fellow and a Senior Member of IMAPS, a member of SPIE, a member of the American Society of Information Science (ASIS), and a member of the Association Computing Machinery (ACM). He is an elected member of the Board of Governors for the IEEE/CPMT Society and is the current Editor-in-Chief and Founding Editor, IEEE Transactions on Electronics Packaging Manufacturing (previously titled: Manufacturing).
As a technology futurist, he has focused his current activities on evaluating emerging trends and applications in nanotechnology, mesomaterials, MEMS/NEMS, and semiconductors with an emphasis on feasibility evaluation and profitable business insertion. His most recent published material is on nanotechnology, cleaning/contamination issues, nano patterning, and cost effective application of technology. He is an IEEE Distinguished Lecturer.

8th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓 🗺

— tutorials, alpha upset, materials selection, process control, case studies …

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Date: Thursday, November 3, 2016
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Juniper Networks, Building 6, 1215 Borregas Ave, Sunnyvale
Attendance: On-site or Remote (WebEx)
Cost: Free
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Juniper Networks; Pure Technologies; Cisco Systems; XIA.

Our annual IEEE Soft Error Rate Workshop, now in its 8th year, focuses on alpha-induced soft errors with its unique offering of simultaneous on-site and remote participation. It provides opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
This year’s event has a new format: We will be inviting industry experts in the field to offer three tutorials on fundamentals of alpha-related soft errors (shown in red below), to bring engineers and managers up to speed, interspersed with three presentations on current issues, solutions and case studies. Note that all times are Pacific Standard Time; please convert, for your location.
For those participating via WebEx on the Internet, we will send log-in information to all registrants on Wednesday, November 2nd.
See summaries of the contents of the tutorials and talks at this location.

Summary

Time (PST) Presenter Title
9:30 AM Check-in and Registration
10:00 AM Eric Crabill, Xilinx Tutorial: An Introduction to Single Event Effects (more)
10:45 AM Adrian Evans, iROC Tutorial: System Design Considerations for Soft Error Mitigation (more)
11:30 AM Rick Wong, Cisco Challenges of Alpha Testing (more)
12:00 Noon Lunch and Exhibits
1:00 PM Brendan McNelly, XIA; Mike Gordon, IBM Tutorial: Techniques and Challenges of Alpha Emissivity Measurements (more)
1:45 PM Laura Monroe, Los Alamos National Lab Resilience and Inexact Computing (more)
2:15 PM Francis Classe, Cypress Soft Error Upset Sensitivity to the Array Background Pattern in SLC Floating Gate and Charge Trapping Flash Memories (more)
2:45 PM Eric Crabill, Xilinx Alpha-Induced Soft Errors in Xilinx UltraScale+ Devices – Not a ‘Material’ Issue (more)
3:30 PM Close of Workshop