Trends and Transitions in Semiconductor Packaging 🗓 🗺

— business models, supply chain, technology requirements, forecast for 2018 and 2019 …

Speaker: Dan Tracy, Senior Director Industry Research & Statistics, SEMI
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Presentation Slides: “Trends and Transitions in Semiconductor Packaging” (1 MB PDF)
Meeting Date: Wednesday, February 14, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1802eps.eventbrite.com
Summary: While on the heels of a strong growth year, there are a number of transitions and inflection points influencing the future of semiconductor packaging. Such trends include changes in business models, a changing supply chain, and packaging technology requirements that are affecting the materials market. This presentation will highlight these changes and transitions, and it will also include the SEMI forecast for packaging material for both 2018 and 2019.


Bio: Dr. Dan Tracy, Sr. Director of Industry Research and Statistics at SEMI, is responsible for developing and executing the global strategy for SEMI industry research and statistics products and services. Current market statistics products include monthly and quarterly data programs covering semiconductor capital equipment, materials and components, with in-depth annual reports on a variety of topics such as packaging materials and trends in the China market. Tracy is responsible for preparing market reports and presenting on trends impacting the electronic materials and equipment markets globally. In addition, Tracy is responsible for managing market statistics partnerships globally.
Prior to joining SEMI in 2000, Tracy was a Research Associate with Rose Associates, a prominent market research and consulting firm specializing in electronics materials. Prior to this, Tracy was employed at National Semiconductor’s Package Technology Group.
Tracy has a Ph.D. in materials engineering from Rensselaer Polytechnic Institute, a M.S in materials science & engineering from Rochester Institute of Technology and a B.S. in chemistry from State University of New York (SUNY) College of Environmental Science and Forestry.

Heterogeneous Packaging Integration for Electronics Systems 🗓 🗺

— mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast …

Speaker: Dr. John H Lau, ASM Pacific Technology
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Presentation Slides: “Fan-Out Wafer-Level Packaging
for 3D IC Heterogeneous Integration”
(3.4 MB PDF)
Meeting Date: Thursday, January 25, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only (no cost): 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1801eps.eventbrite.com

Summary: Because of the drive of Moore’s law, compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. It has been a very “fancy” name in semiconductor packaging for the past few years. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem, rather than integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more implementations of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and lower gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

SoC: Apple’s application processor (A10 and A11)
SiP: Amkor’s SiP for automobiles; Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer): Leti’s SoW; ULCA’s SoW
Heterogeneous Integration with TSV-Interposers: TSMC/Xilinx’s CoWoS; AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer; Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer: Xilinx/SPIL’s TSV-less SLIT; SPIL/Xilinx’s TSV-less NTI; Amkor’s TSV-less SLIM; ASE’s TSV-less FOCoS; MediaTek’s TSV-less RDLs by FOWLP; Intel’s TSV-less EMIB; Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM; Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer; Cisco/eSilicon’s TSV-less Organic Interposer; ITRI’s TSV-less TSH; Shinko’s TSV-less i-THOP


Bio: John H. Lau has been a senior technical advisor of ASM since 2014, an ITRI Fellow of Industrial Technology Research Institute for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at HPLab/Agilent in California for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on flip chip technologies, WLCSP, BGA, TSV for 3D integration, advanced MEMS packaging, and reliability of 2D and 3D IC interconnections. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Comparison of Die Singulation Techniques 🗓 🗺

— die thinning, stealth laser, laser abrasion, plasma etch, rotary blade, results …

Speaker: Dr. Annette Teng, Chief Technology Officer, Promex Industries
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Presentation Slides: “Comparison of Singulation Techniques” (5 MB PDF)
Meeting Date: Thursday, September 28, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1709bcpmt.eventbrite.com
Summary: Wafer thinning and singulation is a critical process for successful miniaturization and high density packaging. A comparison of the latest die singulation techniques will be presented based on dicing yields and cost. These include stealth laser, laser abrasion, plasma etch and conventional rotary blade. Some results of stealth laser on singulated II-VI and III-V type dies will be presented in collaboration with Disco.


Bio: Annette Teng is currently the Chief Technology Officer at Promex Industries, which is a fast-turn subcontractor located in Silicon Valley. She has previously worked in components packaging and assembly at Philips Semiconductor, Linear Technology and Corwil Technology. Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years. She also worked at the Hong Kong University of Science and Technology to initiate their electronics packaging programs in 1997 to 2000. She has been active in IEEE-EPS (CPMT) activities locally and overseas. She is currently the Chair of the IEEE-EPS (CPMT) Santa Clara Valley/Bay Area Chapter.
She graduated with a Ph.D. in Materials Engineering from University of Virginia after receiving a BS from Sweet Briar College.

How to Peel Ultra-Thin Dies from Wafer Tape 🗓 🗺

— bending stress, die strength, peel force, die structures, wafer processing steps, TSVs, pickup methods, experimental verification …

Speaker: Dr. Stefan Behler, Senior Expert Process Engineer, Besi Switzerland AG
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Presentation Slides: “How To Peel Ultra Thin Dies From Wafer Tape” (1 MB PDF)
Meeting Date: Thursday, December 7, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1712cpmt.eventbrite.com
Summary: The four major key properties for successful, damage-free ultra-thin die (< 50 um thick) pickup from a wafer foil are described in detail: die bending stress, die strength, edge peel force, and bulk peel force. First, bending stress for different pickup methods (multi stage, multi disc, multi needle) are calculated and compared using a dynamic FEA model. Second, we summarize how the die strength is influenced by die structures and wafer processing steps, especially by thinning and dicing methods. In addition, we present die strength measurements for TSV test dies. Third, the property "wafer foil edge peel force" is introduced, and the dependency on the dicing method is experimentally verified. It clearly shows, that dicing-before-grinding is to be preferred over single cut dicing. Fourth, we give an overview of bulk peel forces of various commercial wafer foils. Values are taken from datasheet specifications, and compared using Kendall’s equation. Bio: Stefan Behler received his M. S. in experimental physics from the University of Göttingen (Gemany) in 1990, and his Ph.D. in physics from the University of Basel (Switzerland) in 1994. He was awarded an Alexander von Humboldt fellowship for a 2-year research project at the Lawrence Berkeley National Laboratory. The project was aimed at the investigation of surface chemistry of noble metals. In 1996 he joined the company Besi (formerly ESEC) focusing on process technology of die bonding. He is currently project manager for ultra-thin die applications at Besi Switzerland.

Ten Years of Robustness Validation Applied to Power Electronics Components 🗓 🗺

— European car makers, physics of failure, “test to fail”, end-of-life testing, thick wire bonds, planar interconnects …

Speaker: Dr Eckhard Wolfgang, European Center for Power Electronics e.V. (retired from Siemens Research)
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Presentation Slides: “Ten Years of Robustness Validation Applied to Power Electronics Components” (4.3 MB PDF)
Meeting Date: Thursday, April 27, 2017
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1704cpmt.eventbrite.com
Summary: The Robustness Validation process is based on the knowledge of the condition of use (mission profile), the physics of failure, and of acceleration models for lifetime prediction. It provides a “test to fail” qualification instead of “test-to pass”, which results in “Fit for Application”. A Team consisted of German auto carmakers, with 1st and 2nd tiers (power module and DC-link) manufacturers, developed qualification specifications, moderated by ZVEI and ECPE. End-of-life tests play an important role together with lifetime models. Advanced technologies consisting of new materials, such as thick copper wire bonds, or planar interconnect schemes, such as silver-sintered or embedded-sandwich modules, however, will show new failure modes and mechanisms which have to be considered for qualification.


Bio: Dr. Eckhard Wolfgang received his PhD in technical physics from the Technical University Vienna in 1970. In the same year he joined Siemens Research at Munich where he stayed until 2016. From 1989 until 2016 he headed the power electronics department. Since then he is working as a consultant for ECPE e.V. (European Center for Power Electronics), mainly in the field of education (Tutorials, Workshops, Conferences like CIPS).

Advances in Low Cost/High Reliability Lead-Free Solder Materials 🗓 🗺

— solder’s role, compositions, properties, Ag content, optimum cost/reliability, failure modes …

Speaker: Dr. Ning-Cheng Lee, Vice President of Technology, Indium Corporation
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Meeting Date: Thursday, February 23, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation Slides: “Low Cost High Reliability Solder Materials” (1.5 MB PDF)
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1702cpmt.eventbrite.com
Summary: While the electronics industry is advancing rapidly toward miniaturization, two more important drivers actually dictate whether the manufacturers could stay in the game or not — Low Cost, and High Reliability. The former is the ticket to get into the game, while the latter is the ticket to stay in the game. These two drivers exemplified their vital role most astonishingly in solder materials. This talk covers the roles of solder composition on cost, and on reliability. After reviewing the role of Ag in both cost and reliability, the solder materials are reviewed from the lowest cost, zero-Ag solders to composition with higher and higher Ag content. Among all of the alloy options present on the market, including the most recent developments, the representative alloys are introduced with more details, including materials properties, soldering performance, some of the known failure modes, and the primary merit of these alloys.


Bio: Dr. Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has
more than 30 years of experience in the development of fluxes, solder alloys, and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

Intel Silicon Photonics: From Research to Product 🗓 🗺

— optical, SiPh, standard silicon processing, performance, low-cost, optical100G transceiver …

Speaker: Dr. Ling Liao, Principal Engineer, Intel
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Meeting Date: Wednesday, March 8, 2017
Presentation Slides: “Intel Silicon Photonics: From Research to Product” (1.4 MB PDF)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1703acpmt.eventbrite.com
Summary: Silicon photonics is a breakthrough communications technology that brings optical solutions to the computing industry and can revolutionize the data center. It combines the performance benefits of optical communication and manufacturing capability of silicon CMOS to enable high speed, long reach, small form-factor, and low power connectivity. This talk discusses Intel’s work in researching and developing silicon photonics and the announcement of two Intel® Silicon Photonics 100G optical transceivers for data communications applications.


Bio: Dr. Ling Liao is a Principal Engineer in Intel’s Silicon Photonics Product Division. She joined Intel in 1997 and is a pioneer in silicon high-speed modulation and silicon photonic integration. Her work helped establish Intel as a premier leader in Silicon Photonics (SiPh) technology, and it played a big part in transforming SiPh from being a niche technical interest 15 years ago to the now key enabling technology to revolutionize data communication and data centers.

Developing Technology for Autonomous Vehicles and Electric Cars: The Next Platform 🗓 🗺

— half-day Workshop: automotive environment, materials, packaging, devices for 5G, LiDAR, RADAR …

(Links to Slides, Below)
Speakers: Professors and Researchers at Georgia Tech/NSF Packaging Research Center (see below)
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Sponsored by: CPMT Chapter, with Vehicular Technology Chapter, Technology and Engineering Management Chapter, Photonics Chapter
Workshop Date: Friday, March 24, 2017
Time: 12:30 PM Registration and Networking; 1:00 – 5:30 PM Workshop; 5:45 Reception
Cost: $35 IEEE members. students, unemployed, $50 non-members ($15 more at door)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1703cpmt.eventbrite.com
For information about exhibiting your technology at this Workshop, please contact Paul Wesling at 408-320-1105.
Summary: This new era of automotive electronics — such as autonomous driving, in-car smartphone-like infotainment, privacy and security, high-speed and high-bandwidth computing, and all-electric cars — requires an entirely differnt vision than is pursued today. There are unprecedented challenges and opportunities to adress these needs with a systematic approach to system scaling, innovative device and package architectures, and heterogeneous integration for the new era, with particular focus on electrical, mechanical, and thermal designs, and new digital, RF, millimeter wave, LiDAR, camera, high-power and high-temperature electronics technologies.
The challenges in this new era are many, and include not only new technologies, but also an educated workforce, supply chain manufacturing, roadmaps, and standards. This workshop will describe the needs and challenges, as well as review the state-of-the-art in R&D and in manufacturing.

Program and Schedule:

Time Details
12:30 Registration/Sign-In and Networking
1:00 The New Era of Automotive Electronics: The Ultimate Electronics System
Presentation Slides: “The New Era of Automotive Electronics: Intro to GaTech PRC Industry Consortium” (5.2 MB PDF)
Prof. Rao Tummala, Director, NSF Packaging Research Center
infotainment, autonomy, innovative architectures, system scaling, design challenges, roadmaps, manufacturing … [more]
Session 1 Computing and Communications Electronics
1:45 2.5D Glass Interposer For Ultra-high Bandwidth Computing
Presentation Slides: “Glass Packaging R&D” (3.2 MB PDF)
Dr Venky Sundaram and Prof Rao Tummala, Georgia Tech
— 2.5D and 3D integration, large panel processing, low cost interposers, through-glass vias, reliability, compliant interconnections, data centers … [more]
2:15 Low- and Medium-Power Electronics
Presentation Slides: “Power Packaging for Computer Applications” (2 MB PDF)
Dr. Raj Pulugurtha and Prof Rao Tummala, Georgia Tech
— IVR, DC-DC converters, substrate-embedded inductors, transformers and capacitors, high-temp and high-voltage capacitors … [more]
2:45 Coffee, Tea Break; Networking and Exhibitor Interactions
3:15 5G Communications with Glass Embedding and Fanout
Presentation Slides: “5G (28-40 GHz) Substrates and Antennas” (.5 MB PDF) and “5G Communications with Glass Embedding and Fanout” (6 MB PDF)
Prof. Emmanouil Tentzeris, Dr. Venky Sunraram and Dr. Raj Pulugurtha, Georgia Tech
— Advanced 5G substrates, package-integrated antennas, low-loss and precision 5G transmission lines, passive components … [more]
Session 2 Sensing Electronics
3:45 Devices and 3D Glass Fanout Package for Next Generation Radar, Lidar and Camera
Presentation Slides: “Autonomous Cars: Radar, Lidar, Stereo Cameras” (4 MB PDF)
Dr. Venky Sundaram, Dr. Chris Valenta, Prof. Peter Hesketh and Prof. John Cressler, Georgia Tech
— sensor fusion, SiGe devices, low-cost LiDAR packaging, hermetic and near-hermetic glass packages for sensors, design for reliability … [more]
Session 3 Devices, Packaging and High-Temperature Materials for Power Electronics in Electric Cars
4:15 High-Power and High-Temperature Electronics for Electric Cars
Presentation Slides: “High-Power Devices, High-Temperature Materials and Packaging for Electric Cars” (5 MB PDF)
Prof. Shyh-Chiang Shen, Dr. Vanessa Smet and Dr. Raj Pulugurtha, Georgia Tech
— Packaging for 150-250 C, high-temp dielectrics and mold compounds, high-temp substrates and fan-out packages … [more]
5:00
Experts
Panel
Moderator: Paul Wesling
— Questions, observations, future directions
5:45
Reception
Refreshments and Networking
— snacks and drinks
— Meet our exhibitors
— Consult with the speakers
6:30 Dismissal

Wafer-Level Process Formation of a Polymer-Isolated Chip-Scale Package 🗓 🗺

— yield loss, leakage, sidewall insulation, protection, reliability results …

Speaker: Harry Gee, ON Semiconductor
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Presentation Slides: “Wafer-Level Process Formation of a Polymer-Isolated Chip-Scale Package” (1 MB PDF)
Meeting Date: Tuesday, November 22, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1611cpmt.eventbrite.com
Summary: Small-footprint (0201/01005 size) bare silicon chip-scale package (CSP) after board assembly has yield loss due to high leakage between an I/O pad and the silicon substrate. The solder paste applied at assembly can inadvertently extend out and touch the exposed silicon along the sidewall of the CSP device. After reflow, this excess solder may cause a high leakage path or short between an I/O pad and the silicon of the CSP device. Small-footprint CSP devices normally have I/O pads that are short and close to the CSP die edge. The short bump height and the proximity to the die edge increase the chance for a solder short to the silicon substrate along the sidewall. In this talk, we present a wafer-level backend process flow to make a 0201/01005 CSP device such that the silicon sidewalls and backside are completely covered by a thin non-conducting polymer material. The polymer-isolated CSP solution provides complete electrical insulation to the active silicon. This eliminates solder-to-silicon sidewall leakage yield loss after board assembly. The polymer offers protection to the active silicon device from assembly handling to prevent die cracking and chip-out. We will present assembly electrical yield and board level reliability results for this polymer-isolated CSP device made by wafer level processing.
Bio: Harry Gee is presently a Device Engineer at ON Semiconductor. He received his B.S. degree in Chemical Engineering from the University of California, Berkeley. He has been active in the semiconductor industry for over thirty years as Process, Device, and Development engineer. He has worked with Wafer-Level Chip-Scale Packaging (WLCSP) for the past sixteen years on numerous products from discrete parts to large analog/logic chips.

Advances in Plasma Nano-coating 🗓 🗺

— properties, density, pinhole-free, thicknesses, corrosion resistant, environmentally benign …

Speaker: Abe Ghanbari PhD, Chief Solutions Officer, Semblant
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Presentation Slides: “Advances in Plasma Nano-coating” (3 MB PDF)
Meeting Date: Tuesday, November 8, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1611lcpmt.eventbrite.com
Summary: Plasma nano-coatings, due to their inherently superior properties, are rapidly finding new applications in a multitude of industries. This includes consumer electronics, automotive, industrial, semiconductor and medical.
In plasma coating, a nano-scale organic or inorganic layer is formed over the entire surface area of an object placed in the plasma. The coating process is relatively simple and does not require any curing once the coating is completed. In general, the coatings tend to be highly dense and pinhole-free. Most of the coatings produced are colorless and odorless and can be easily formed with thicknesses ranging from 100s of Å to several µ. The coatings adhere to variety of substrate materials on an atomic scale and do not affect the look and feel of the substrates.
By developing the right combination of plasma coating technology and polymers, we have been able to achieve multi-layer liquid repellent, galvanic corrosion resistance and environmentally benign coatings. In this presentation, we will describe the technology and process of our PlasmaShield® with high volume mass production traction characteristics in enhancing the reliability of the devices used in consumer electronics.


Bio: Dr. Abe Ghanbari is Chief Solutions Officer at Semblant since 2012. Prior to Semblant, Abe was VP at NovaSolar Technologies, where he led development and deployment of solar processing technologies and equipment for China’s factory. Abe started his career in R&D at Varian Corporation, followed by a variety of product development and general management roles at Sony, Applied Materials and VLOC Corp. He currently serves on the advisory board of several technology centers, start-ups and well-established companies. Throughout his career, he has developed technologies, products and processes that provide solutions to meet the needs of customers in emerging markets.
Abe holds a Ph.D. in engineering & applied physics, Cornell University, M.S. in plasma science, and B.S. in electrical engineering from the University of Illinois, M.B.A. from Saint Mary’s College with emphasis in operations and marketing, management. He is a holder of eight patents.