Visualizing the Packaging Roadmap 🗓 🗺

— ITRS, Moore’s Law, innovation, roadmaps, packaging issues, hi-performance computing, solutions …

Speaker: Ivor Barber, Corporate VP for Packaging, AMD
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Presentation Slides: “Visualizing the Packaging Roadmap” (1.7 MB PDF)
Meeting Date: Wednesday, March 13, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE/MEPTEC members students, unemployed; $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Reservations: 1903eps.eventbrite.com
Co-sponsor:
Summary: With the end of Moore’s Law as an economic driver at 28nm, and publication of the final edition of the ITRS in July 2016, we find packaging is now on the center stage of semiconductor innovation — but what roadmap do we follow? This presentation will discuss prior roadmaps and how the packaging industry is responding with a product-based integrated solution roadmap. The presenter will discuss the goals of Heterogeneous Integration for High Performance Computing Applications and the packaging solutions this will drive.

Bio: Ivor Barber is currently Corporate VP for Packaging at AMD with responsibility for all Packaging activity from Design through High Volume Manufacturing. With over 35 years experience in the Semiconductor Industry, Ivor has held various Engineering and Management positions in Assembly, Package Characterization and Package Design at National Semiconductor, Fairchild Semiconductor, VLSI Technology, LSI Corporation and Xilinx. Ivor graduated from Napier University in Edinburgh, Scotland with a Bachelors degree in Technology and holds 15 US patents related to packaging.

FPGA Heterogeneous Packaging Applications: Trends and Challenges 🗓 🗺

— HPC, networking, cloud services, automotive, logic/memory integration, thermal, evolution …

Co-sponsored by the Solid State Circuits Chapter
Speaker: Suresh Ramalingam, PhD., Fellow, Manager Advanced Packaging Interconnect Technology Development, Xilinx
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Presentation Slides: “FPGA Heterogeneous Packaging Applications: Trends and Challenges” (1.6 MB PDF)
Meeting Date: Wednesday, November 14, 2018
Time: 11:30 AM Registration (and pizza/water); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1811eps.eventbrite.com

Summary: Deep learning and artificial intelligence are at the heart of today’s technological innovations. Driven by advanced applications in HPC (High Performance Computing), Networking, Cloud Services and Automotive, demand for high bandwidth, lower latency and lower system power solutions have gained a lot of interest and momentum. As HPC designs move to several TB/sec and Telecom pushes to 400G/800G systems, bottlenecks in lower-latency memory bandwidth require HBM (High Bandwidth DRAM Memory) integration.
Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out InFO or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in a package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solutions are also becoming an active area of focus as the power levels are expected to push beyond 500W.
In this presentation we will examine FPGA Heterogeneous Packaging evolution working together with TSMC, industry trends and challenges. Since a system-level perspective is very important, we will touch upon some of the mechanical and thermal challenges and trends, and interplay with the package.

Bio: Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from the Massachusetts Institute of Technology. He holds 24 US Patents, the 2013 SEMI Award, the Ross Freeman Award for Technical Innovation, ECTC 2011’s Conference Best Paper Award, and IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D. He started his career at Intel developing Organic Flip Chip Technology for microprocessors which was implemented on Pentium I (Intel’s first flip chip product for laptops) in 1997. As one of the co-founders and Director of Packaging Materials at Scion Photonics, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D for Xilinx FPGA products.

The Road Ahead: Outlook for the Electronics Packaging Industry 🗓 🗺

— projections for AI, autonomous vehicles, crypto, OSATs, foundries, outlook …

Speaker: E. Jan Vardaman, President, TechSearch International, Inc.
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Presentation Slides: “The Road Ahead: Outlook for the Industry” (2 MB PDF)
Meeting Date: Monday, October 22, 2018
Time: 12:30 PM Registration, lunch, and presentation (ending at 2:30 PM)
Cost: $25

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: fs24.formsite.com/meptec/form171
Summary: The semiconductor industry has seen record growth in the last few years, but with slowing growth in smartphone shipments and PC sales, what’s next? What will drive growth in advanced packaging? Is it Game Over for Cryptocurrency? Artificial Intelligence and automotive electronics are bright spots, but what types of packages will be used? How will OSATs benefit and what role will the foundry play? This presentation will examine economic and technology trends and provides an outlook for the industry.


Bio: Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia, and on the US mission to study manufacturing in China. She is a member of IEEE EPS, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE EPS Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

2D to 3D Package Architectures: Back to the Future 🗓 🗺

— scaling, heterogeneous integration, impact on power, performance, latency, nomenclature for package architectures, current metrics, projections …

Speaker: Dr. Raja Swaminathan, Package Architect
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Presentation Slides: “2D to 3D Package Architectures: Back to the Future” (1.5 MB PDF)
Meeting Date: Thursday, May 3, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: (URL) 1805aeps.eventbrite.com
Summary: Moore’s Law Scaling has driven electronics industry growth and new package architectures (including 3D architectures and architectures currently defined as 2.1D, 2.3D or 2.5D architectures) are projected to be major enablers to maintain the pace of Moore’s law scaling and enable heterogeneous integration. Historically, packaging has scaled sufficiently to act as a space and electrical transformer to enable transistor/silicon scaling, and innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. With an increasing drive for heterogeneous integration, packaging is being increasingly challenged to deliver power-efficient, high bandwidth on/off package low power links and meet diverse functionality ranging from high performance servers to flexible, wearable electronics. This talk will introduce a new IEEE standardized industry nomenclature on package architectures covering and clearly demarcating both 2D and 3D constructions, as well as highlight the key metrics driving the evolution of these architectures, their current values (based on the state of the art) and projections for the next 5-10 years. This is expected to drive focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next generation requirements in the 2D-3D architecture space.

Bio: Dr. Raja Swaminathan is an IEEE senior member and was a package architect at Intel for next generation server, client and mobile products. His expertise is on delivering integrated HVM-friendly package architectures with optimized electrical, mechanical, and thermal solutions. He is an IEEE, ITRS and iNEMI Roadmap author on packaging and design, and recently drove industry convergence of 2D and 3D architecture nomenclatures and design, process and electrical metrics. He has also served on IEEE micro-electronics and magnetics technical committees and has been key note speaker in electronics conferences. He has 26 patents and 25 peer-reviewed publications and holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University.

Trends and Transitions in Semiconductor Packaging 🗓 🗺

— business models, supply chain, technology requirements, forecast for 2018 and 2019 …

Speaker: Dan Tracy, Senior Director Industry Research & Statistics, SEMI
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Presentation Slides: “Trends and Transitions in Semiconductor Packaging” (1 MB PDF)
Meeting Date: Wednesday, February 14, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1802eps.eventbrite.com
Summary: While on the heels of a strong growth year, there are a number of transitions and inflection points influencing the future of semiconductor packaging. Such trends include changes in business models, a changing supply chain, and packaging technology requirements that are affecting the materials market. This presentation will highlight these changes and transitions, and it will also include the SEMI forecast for packaging material for both 2018 and 2019.


Bio: Dr. Dan Tracy, Sr. Director of Industry Research and Statistics at SEMI, is responsible for developing and executing the global strategy for SEMI industry research and statistics products and services. Current market statistics products include monthly and quarterly data programs covering semiconductor capital equipment, materials and components, with in-depth annual reports on a variety of topics such as packaging materials and trends in the China market. Tracy is responsible for preparing market reports and presenting on trends impacting the electronic materials and equipment markets globally. In addition, Tracy is responsible for managing market statistics partnerships globally.
Prior to joining SEMI in 2000, Tracy was a Research Associate with Rose Associates, a prominent market research and consulting firm specializing in electronics materials. Prior to this, Tracy was employed at National Semiconductor’s Package Technology Group.
Tracy has a Ph.D. in materials engineering from Rensselaer Polytechnic Institute, a M.S in materials science & engineering from Rochester Institute of Technology and a B.S. in chemistry from State University of New York (SUNY) College of Environmental Science and Forestry.

Heterogeneous Packaging Integration for Electronics Systems 🗓 🗺

— mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast …

Speaker: Dr. John H Lau, ASM Pacific Technology
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Presentation Slides: “Fan-Out Wafer-Level Packaging
for 3D IC Heterogeneous Integration”
(3.4 MB PDF)
Meeting Date: Thursday, January 25, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only (no cost): 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1801eps.eventbrite.com

Summary: Because of the drive of Moore’s law, compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. It has been a very “fancy” name in semiconductor packaging for the past few years. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem, rather than integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more implementations of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and lower gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

SoC: Apple’s application processor (A10 and A11)
SiP: Amkor’s SiP for automobiles; Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer): Leti’s SoW; ULCA’s SoW
Heterogeneous Integration with TSV-Interposers: TSMC/Xilinx’s CoWoS; AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer; Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer: Xilinx/SPIL’s TSV-less SLIT; SPIL/Xilinx’s TSV-less NTI; Amkor’s TSV-less SLIM; ASE’s TSV-less FOCoS; MediaTek’s TSV-less RDLs by FOWLP; Intel’s TSV-less EMIB; Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM; Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer; Cisco/eSilicon’s TSV-less Organic Interposer; ITRI’s TSV-less TSH; Shinko’s TSV-less i-THOP


Bio: John H. Lau has been a senior technical advisor of ASM since 2014, an ITRI Fellow of Industrial Technology Research Institute for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at HPLab/Agilent in California for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on flip chip technologies, WLCSP, BGA, TSV for 3D integration, advanced MEMS packaging, and reliability of 2D and 3D IC interconnections. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Comparison of Die Singulation Techniques 🗓 🗺

— die thinning, stealth laser, laser abrasion, plasma etch, rotary blade, results …

Speaker: Dr. Annette Teng, Chief Technology Officer, Promex Industries
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Presentation Slides: “Comparison of Singulation Techniques” (5 MB PDF)
Meeting Date: Thursday, September 28, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1709bcpmt.eventbrite.com
Summary: Wafer thinning and singulation is a critical process for successful miniaturization and high density packaging. A comparison of the latest die singulation techniques will be presented based on dicing yields and cost. These include stealth laser, laser abrasion, plasma etch and conventional rotary blade. Some results of stealth laser on singulated II-VI and III-V type dies will be presented in collaboration with Disco.


Bio: Annette Teng is currently the Chief Technology Officer at Promex Industries, which is a fast-turn subcontractor located in Silicon Valley. She has previously worked in components packaging and assembly at Philips Semiconductor, Linear Technology and Corwil Technology. Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years. She also worked at the Hong Kong University of Science and Technology to initiate their electronics packaging programs in 1997 to 2000. She has been active in IEEE-EPS (CPMT) activities locally and overseas. She is currently the Chair of the IEEE-EPS (CPMT) Santa Clara Valley/Bay Area Chapter.
She graduated with a Ph.D. in Materials Engineering from University of Virginia after receiving a BS from Sweet Briar College.

How to Peel Ultra-Thin Dies from Wafer Tape 🗓 🗺

— bending stress, die strength, peel force, die structures, wafer processing steps, TSVs, pickup methods, experimental verification …

Speaker: Dr. Stefan Behler, Senior Expert Process Engineer, Besi Switzerland AG
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Presentation Slides: “How To Peel Ultra Thin Dies From Wafer Tape” (1 MB PDF)
Meeting Date: Thursday, December 7, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1712cpmt.eventbrite.com
Summary: The four major key properties for successful, damage-free ultra-thin die (< 50 um thick) pickup from a wafer foil are described in detail: die bending stress, die strength, edge peel force, and bulk peel force. First, bending stress for different pickup methods (multi stage, multi disc, multi needle) are calculated and compared using a dynamic FEA model. Second, we summarize how the die strength is influenced by die structures and wafer processing steps, especially by thinning and dicing methods. In addition, we present die strength measurements for TSV test dies. Third, the property "wafer foil edge peel force" is introduced, and the dependency on the dicing method is experimentally verified. It clearly shows, that dicing-before-grinding is to be preferred over single cut dicing. Fourth, we give an overview of bulk peel forces of various commercial wafer foils. Values are taken from datasheet specifications, and compared using Kendall’s equation. Bio: Stefan Behler received his M. S. in experimental physics from the University of Göttingen (Gemany) in 1990, and his Ph.D. in physics from the University of Basel (Switzerland) in 1994. He was awarded an Alexander von Humboldt fellowship for a 2-year research project at the Lawrence Berkeley National Laboratory. The project was aimed at the investigation of surface chemistry of noble metals. In 1996 he joined the company Besi (formerly ESEC) focusing on process technology of die bonding. He is currently project manager for ultra-thin die applications at Besi Switzerland.

Ten Years of Robustness Validation Applied to Power Electronics Components 🗓 🗺

— European car makers, physics of failure, “test to fail”, end-of-life testing, thick wire bonds, planar interconnects …

Speaker: Dr Eckhard Wolfgang, European Center for Power Electronics e.V. (retired from Siemens Research)
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Presentation Slides: “Ten Years of Robustness Validation Applied to Power Electronics Components” (4.3 MB PDF)
Meeting Date: Thursday, April 27, 2017
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1704cpmt.eventbrite.com
Summary: The Robustness Validation process is based on the knowledge of the condition of use (mission profile), the physics of failure, and of acceleration models for lifetime prediction. It provides a “test to fail” qualification instead of “test-to pass”, which results in “Fit for Application”. A Team consisted of German auto carmakers, with 1st and 2nd tiers (power module and DC-link) manufacturers, developed qualification specifications, moderated by ZVEI and ECPE. End-of-life tests play an important role together with lifetime models. Advanced technologies consisting of new materials, such as thick copper wire bonds, or planar interconnect schemes, such as silver-sintered or embedded-sandwich modules, however, will show new failure modes and mechanisms which have to be considered for qualification.


Bio: Dr. Eckhard Wolfgang received his PhD in technical physics from the Technical University Vienna in 1970. In the same year he joined Siemens Research at Munich where he stayed until 2016. From 1989 until 2016 he headed the power electronics department. Since then he is working as a consultant for ECPE e.V. (European Center for Power Electronics), mainly in the field of education (Tutorials, Workshops, Conferences like CIPS).

Advances in Low Cost/High Reliability Lead-Free Solder Materials 🗓 🗺

— solder’s role, compositions, properties, Ag content, optimum cost/reliability, failure modes …

Speaker: Dr. Ning-Cheng Lee, Vice President of Technology, Indium Corporation
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Meeting Date: Thursday, February 23, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation Slides: “Low Cost High Reliability Solder Materials” (1.5 MB PDF)
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1702cpmt.eventbrite.com
Summary: While the electronics industry is advancing rapidly toward miniaturization, two more important drivers actually dictate whether the manufacturers could stay in the game or not — Low Cost, and High Reliability. The former is the ticket to get into the game, while the latter is the ticket to stay in the game. These two drivers exemplified their vital role most astonishingly in solder materials. This talk covers the roles of solder composition on cost, and on reliability. After reviewing the role of Ag in both cost and reliability, the solder materials are reviewed from the lowest cost, zero-Ag solders to composition with higher and higher Ag content. Among all of the alloy options present on the market, including the most recent developments, the representative alloys are introduced with more details, including materials properties, soldering performance, some of the known failure modes, and the primary merit of these alloys.


Bio: Dr. Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has
more than 30 years of experience in the development of fluxes, solder alloys, and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.