IEEE Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) 🗓

— scientific and engineering exploration of thermal, thermomechanical and emerging technology issues …

The IEEE Electronics Packaging Society’s premiere thermal design/modeling conference.
register
Dates: May 26-29, 2020
Location: The Cosmopolitan Hotel, Las Vegas, NV
The ITherm Conference series is the leading international venue for scientific and engineering exploration of thermal, thermomechanical, and emerging technology issues associated with electronic devices, packages, and systems. In addition to paper presentations and vendor exhibits, ITherm 2019 will have panel discussions, keynote lectures by prominent speakers, invited Tech Talks, and professional short courses. Co-located with ECTC. Download the Advance Program.
Full information here: www.ieee-itherm.net

IEEE 70th Electronic Components and Technology Conference (ECTC) 🗓

— the best in packaging, components and microelectronic systems science, technology and education …

The IEEE Electronics Packaging Society’s premiere technology conference.
register
Dates: May 26-29, 2020
Location: The Cosmopolitan of Las Vegas, Las Vegas, NV
ECTC is the premier international conference covering a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation. Includes short courses, 40 sessions, co-located with ITherm. Download the Advance Program.
Full information here: www.ectc.net

Heterogeneous Integration Roadmap: 3rd Annual Meeting 🗓 🗺

— future of mobile, HPC, automotive, 5G, health, Chiplets, work on 2020 Roadmap …

register
Dates: Thursday, February 20, 2020 (8:30 AM – 6:00 PM) and Friday, February 21, 2020 (8:30 AM – 4:00 PM)
Cost: $70 General Admission; $60 IEEE/ASME members and employees of SEMI member companies; $35 for retired, unemployed; free for full-time students. includes 2 lunches, wine-tasting
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas CA USA
Information and Reservations: 2002symp-eps.eventbrite.com

NOTE: No photographs or videos are allowed during the Symposium. (This announcement complies with IEEE policies.)
Program Outline: (details below)
Day 1: From the 2019 Roadmap to HIR 2020
— Plenary Speakers from Intel and Google, with views of the future
— Moderated Sessions on the Released Roadmap and what comes next
— California Wine tasting
Day 2: TWG Working Group Workshop for HIR 2020
— Special Forum on the Rise of Chiplets
— Working Group breakout Sessions for HIR 2020
— Cross-Working Group Collaboration meetings

Roadmap Sponsors:

Summary: We are entering the era of the digital economy and ubiquitous connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into our global society, and the plateauing of CMOS’s scaling advantage, continued progress now requires a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
The Heterogeneous Integration Roadmap (HIR) published in 2019 is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). This is a pre-competitive technology roadmap addressing this future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and our professional careers.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have released this new Roadmap — a broad and inclusive worldview that comprehends this diversity, developed by a group of leading technical experts. It was made available in 2019 for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, Feb 20, 2020: Implementation of HIR v1.0; Work on v2.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00 – 9:10: Start of Program; Welcome by Ajit Manocha, SEMI CEO, and Nicky Lu, Etron Chairman
9:10: HIR Symposium Objective
9:25 – 9:55: Plenary Speaker: Virtuous Cycle of AI, Dr Pradeep Dubey, Intel Senior Fellow & Director, Intel Parallel Computing Lab
10:05 – 11:05: Session 1 – Heterogeneous Integration for Communications, Chair: Amr Helmy, Univ of Toronto & IEEE Photonics Society
— 5G, RF and Analog Mixed Signal: Tim Lee (Boeing), Herbert Bennett (Alta Tech)
— Mobile: William Chen (ASE), Benson Chan (Binghamton University)
— Aerospace & Defense: Tim Lee (Boeing), Jeff Demmin (Keysight)
— WLP (Fan-in & Fan-Out): Rozalia Beica (iNEMI), John Hunt (ASE)
— Simulation: Chris Bailey (University of Greenwich), Xuejun Fan (Lamar University)
— Materials & Emerging Research Materials: Bill Bottoms (3MTS)
11:05 – 11:15: Q&A
BREAK
11:30 – 12:20: Session 2 – Heterogeneous Integration for Consumer & Industrial Applications, Chair: Ravi Mahajan, ASME EPPD & Intel
— Medical, Health & Wearables: Mark Poliks (Binghamton U), Nancy Stoffel (GE)
— SiP & Module: Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon), Erik Jung (IZM)
— Single Chip and Multi Chip Integration: William Chen (ASE), Annette Teng (Promex)
— Emerging Research Devices: Meyya Meyyappan (NASA Ames)
— Co-Design: Jose Schutt-Aine (University of Illinois)
12:20 – 12:30: Q&A
12:30 – 12:35: Thanks to Organizers and Patrons
12:35 – 1:30: LUNCH   (box lunch) and discussion time
1:30 – 2:00: Plenary Speaker: Dr. Hong Liu, The Role of Optics in Compute Infrastructure, Distinguished Engineer & Senior Director, Google Technical Infrastructure
2:00 – 2:50: Session 3 – Heterogeneous Integration for High-Performance Computing, Chair: Bill Bottoms, IEEE EPS & 3MTS
— High Performance Computing & Data Centers: Kanad Ghose (Binghamton University), Dale Becker (IBM), Rockwell Hsu (Cisco)
— 2D-3D & Interconnect: Ravi Mahajan (Intel), Subramanian Iyer (UCLA)
— Thermal Management: Madhusudan Iyenger (Google), Azmat Malik (Acuventures)
— Integrated Photonics: Amr Helmy (University of Toronto), Bill Bottoms (3MTS)
— Test: David Armstrong (Adventest)
2:50 – 3:00: Q&A
BREAK
3:15 – 4:15: Session 4 – Heterogeneous Integration for Special Applications, Chair: Tom Salmon, SEMI
— Automotive: Urmi Ray (iNEMI), Rich Rice (ASE)
— MEMS & Sensor Integration: Shafi Saiyed (ADI)
— Integrated Power Packaging: Patrick McCluskey (U-Md), Doug Hopkins (NCSU)
— Cyber Security: Sohrab Aftabjahani (Intel)
— Supply Chain: Paul Trio (SEMI)
— IoT: Robert Lo (ITRI)
4:15 – 4:25: Q&A
4:25 – 5:20: HIR Open Forum: Feedback & Comments
5:20 – 5:35: Next-Day TWG Workshop Preparation
Symposium Closing
5:45 – 6:45: California Wine Tasting

Friday, Feb 21, 2020: HIR Technical Working Group Workshop
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30 – 9:00: Registration and coffee at SEMI Hdqtrs, Milpitas
9:00 – 9:20: All-HIR TWG Overview; HIR 2020 Revision Preparation
9:20 – 10:00: “The Rise of Chiplets” Special Forum
— Invited Speakers: David Kehlet (Intel), Babi Vinnakota (ODSA)
10:00 – 11:30: TWG Breakout Workshop I
11:30 – 12:00: All-TWG Breakout Session Report
12:00: Lunch (box lunches provided)
1:00 – 1:30: Planning for ECTC HIR Workshop & 2020 HIR Events
1:30 – 3:00: TWG Breakout Workshop II
3:00 – 3:30: All-TWG Breakout Session Report
3:30 – 4:00: Closing Remarks and Wrap-Up
4:00 – 5:30: Space available for TWG informal discussions and Cross-TWG collaborations (optional)

Hosted by SEMI   SEMI 
(The first day had been planned for Samsung Foundry; however, due to an abundance of caution relating to staff and visitor health, Samsung has decided to limit large events on their San Jose campus. Our thanks to Samsung for their willingness to host.)
Health Alerts:
— please do not attend if you have been in China (excludes Taiwan) in the last 15 days. We will refund.
— please do not attend if you are not feeling well. We will refund.
— We are expecting a full house and are taking precautions to keep us all healthy. Avoid handshakes (try a fist-bump or short bow). Hand sanitizers will be provided. Microphones will be sterilized.

We thank our Annual Meeting supporters for 2020:
        GOOGLE     Cisco Silitronics


IEEE Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) 🗓

— scientific and engineering exploration of thermal, thermomechanical and emerging technology issues …

The IEEE Electronics Packaging Society’s premiere thermal design/modeling conference.
register
Dates: May 28-31, 2019
Location: The Cosmopolitan Hotel, Las Vegas, NV
The ITherm Conference series is the leading international venue for scientific and engineering exploration of thermal, thermomechanical, and emerging technology issues associated with electronic devices, packages, and systems. In addition to paper presentations and vendor exhibits, ITherm 2019 will have panel discussions, keynote lectures by prominent speakers, invited Tech Talks, and professional short courses. Co-located with ECTC. Download the Advance Program.
Full information here: www.ieee-itherm.net

IEEE 69th Electronic Components and Technology Conference (ECTC) 🗓

— the best in packaging, components and microelectronic systems science, technology and education …

The IEEE Electronics Packaging Society’s premiere technology conference.
register
Dates: May 28-31, 2019
Location: The Cosmopolitan of Las Vegas, Las Vegas, NV
ECTC is the premier international conference covering a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation. Includes short courses, 40 sessions, co-located with ITherm. Download the Advance Program.
Full information here: www.ectc.net

Heterogeneous Integration Roadmap 2-Day Symposium 🗓 🗺

— 2nd Annual, intro to HIR v1.0, overviews, integration, working groups, participation …

register
Dates: Thursday, 21 February 2019 (8:30 AM – 6:00 PM) and Friday 22 February (8:30 AM – 4:00 PM)
Cost: $50 General Admission; $35 IEEE/ASME members and employees of SEMI member companies; $35 for students, unemployed, retired.

Location: SEMI International Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1902symp-eps.eventbrite.com

Program Outline: (details below)
Download Full Program, Hotel Recommendations
NOTE: No photographs or videos will be allowed during the Symposium. (This announcement complies with IEEE policies.)
Day 1: Introduction to HIR v1.0
— Release of HIR version 1.0: How to Download and Use the Roadmap
— Presentations from HIR Technical Working Group chairs
Day 2: TWG Breakout Sessions for HIR v2.0 (TWG Caucus & Cross-TWG meetings)

Sponsors:

We thank our financial supporters for 2019:
     



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.

A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity, and assembled a group of leading technical experts to develop this Roadmap. The first work product of the Roadmap team is being presented by the chairs of the 20 Technical Working Groups. This Version 1.0 is now being released, for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, 21 February 2019: Introduction to HIR v1.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00: Start of Program: Welcome – Ajit Manocha, President & CEO, SEMI Int’l
9:15 – 10:50 AM – Session 1 – Heterogeneous Integration for High Performance
                Chair: Bill Bottoms, EPS and 3MTS
    — High Performance Computing & Data Center, Kanad Ghose (Binghamton U), Dale Becker (IBM)
    — 3D and Interconnect, Ravi Mahajan (Intel)
    — Thermal Management, Madhu Iyenger (Google), Azmat Malik (Acuventures)
    — Integrated Photonics, Amr Helmy (U-Toronto), Bill Bottoms (3MTS)
    — WLP (fan-in and fan-out), Rozalia Beica (DOW), John Hunt (ASE)
    — Test, Dave Armstrong (Advantest)
BREAK
11:00 – 12:30 PM – Session 2 – Heterogeneous Integration for Consumer and Industrial Applications
                Chair: Subu Iyer, UCLA
    — Emerging Devices, Meyya Meyyappan (NASA Ames)
    — Medical, Health and Wearables, Mark Poliks (Binghamton U), Nancy Stoffel (GE), Benson Chan (Binghamton U)
    — SiP & Modules, Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon)
    — Single Chip and Multi Chip Integration, William Chen (ASE), Annette Teng (Promex)
    — Integrated Power Packaging, Patrick McClusky (UMD), Doug Hopkins (NCSU)
    — IoT, Robert Lo (ITRI Taiwan)
12:30 PM – Hosts Recognition; Symposium Sponsor Thank You
12:40 – 1:40 PM – LUNCH     (discussions; box lunch included)
1:40 – 2:25 PM – PLENARY PRESENTATION
Invited Speaker: Babak Sabi, Corporate Vice President, General Manager of Assembly & Test Development, Intel Corporation
2:25 – 3:45 PM -Session 3 – Heterogeneous Integration for Special Applications
                Chair: Tom Salmon, SEMI
    — Aerospace and Defense, Tim Lee (Boeing)
    — 5G in RF and Analog Mixed Signal, Tim Lee (Boeing), Herbert Bennett (Alta Tech)
    — Cyber Security, Sohrab Aftabjahani (Intel)
    — Simulation, Richard Rao (Microsemi), Chris Bailey (U-Greenwich), Xuejun Fan (Lamar U)
    — Co-Design, Jose Schutt-Aine (U of Illinois)
    — MEMS and Sensor Integration, Shafi Saiyed (ADI)
BREAK
4:00 – 5:15 PM – Session 4 – Heterogeneous Integration Applications, Materials & Simulation
                Chair: Amr Helmy, Univ of Toronto
    — Automotive, Urmi Ray (STATS ChipPAC), Rich Rice (ASE)
    — Mobile, William Chen (ASE)
    — Materials and Emerging Research Materials, Bill Bottoms (3MTS)
    — Supply Chain, Tom Salmon (SEMI)
5:15 PM – Information on Release of HIR version 1.0; Download & Roadmap Use
5:30 PM – WRAP UP: Nicky Lu, CEO and Chairman, Etron Technology Inc.
5:45 – 6:45 PM Reception, Social
Wine-tasting and sampling many fine wines from Napa Valley with bartender John Friedlund

Friday, 22 February 2019: TWG Breakout Sessions for HIR & Open House v2.0
Who should attend: All HIR Technical Working Group members and anyone interested in participating or learning more about the Heterogeneous Integration Roadmap and participating in interaction, collaboration and feedback.
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30: Registration and refreshments
9:00: HIR Business:     — Completion of manuscript: Full Roadmaps & White Papers     — HIR 1.0 Release plan     — Peer Review     — Chapters Complete     — Download Schedules     — Planning for HIR 2.0     — 2019 Events: ECTC Las Vegas, SEMICON West, Asia, Europe
10:30: Breakout Sessions A and B, TWG Exchange Caucuses
Lunch (box lunches provided)
1:00 PM – Breakout Sessions C and D, TWG Exchange Caucuses
2:30 PM – Wrap-Up

10th Annual IEEE EPS SCV Soft Error Rate (SER) Workshop 🗓

— alpha upset, materials selection, process control, tutorial, test facilities, case studies …

register
Date: Wednesday, October 24, 2018
Time: 8:30 am – 4:30 pm (PT) (Lunch will be provided)
Location: Xilinx, 2100 All Programmable Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Cost: none
Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.

Our annual IEEE Soft Error Rate Workshop will enter its 10th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue with the format used in the previous two years, with invitied industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
(All times shown are Pacific Daylight Time, California)

Time (PDT) Presenter Title
8:15 AM Check-in and Registration WebEx: Login information will be sent to registrants on Monday, October 22.
8:35 AM Paul Muller, IBM Multi Bit Upset Mitigation Using the Fall Off Curve (more)
9:05 AM Chamkaur Ghag, University College London Ultra-Low Background Radioassay Facilities at the Boulby Underground Laboratory (more)
9:35 AM Joe Hupcey, Mentor Exhaustively Verify EDAC Protected State Machines and Memories Using Formal Verification (more)
10:15 AM Paula Chen, Xilinx 64 MeV Proton Single-Event Evaluation of Xilinx 20nm DDR4-IO Design (more)
10:45 AM Sang Hoon Jeon, HanYang University Logic Upsets in DDR4 SDRAMs Using 480 MeV Protons (more)
11:15 AM Robert Baumann, Radiosity Solutions Making the Grade: From COTS to Space-grade Electronics (more)
12:15 – 12:45 PM Lunch and Discussions (Lunch will be provided)
12:45 PM Eric Prebys, UC Davis The Crocker Nuclear Laboratory (more)
1:15 PM Mark Hanhardt, Sanford Underground Research Opportunities at Sanford Underground Research Facility (more)
1:45 PM Krishna Mohan, GlobalFoundries Demonstration of Soft Error Rate Robustness with Process Improvements and Material Changes – Case Studies (more)
2:15 PM Balaji Narasimhan, Broadcom Soft Errors: From Technology Trends to System-Level Performance (more)
3:00 PM Y. Sawada, MMC Development of High-Precision and Sensitive 2? Gas Flow-Type Alpha Particle Counter (more)
3:30 PM Phil Oldiges, IBM Physics-Inspired Spreadsheet Models for Latch and SRAM SER Screening (more)
4:00 PM Vinod Ambrose, Intel Soft Error Rate Measurements in Solid State Drives (more)
4:30 PM Close of Workshop

View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations

Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, October 22.

Organizers:
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Charlie Slayman, Cisco Systems, Inc.
K. Paul Muller, IBM
Norbert Seifert, Intel
Shomir Dighe, Paul Wesling, Santa Clara Valley EPS Chapter
Vijay Narasimhan, Jin-woo Han, Santa Clara Valley EDS Chapter

Contact us: 2018 SER Workshop

InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) 🗓

— the Electronics Packaging Society’s Key Thermal Conference …

Dates: May 31 – June 3, 2016
Location: Sheraton Hotel, San Diego, CA USA
Summary: The international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems.
— Information and Registration: www.ieee-itherm.net
— Save $100 through May 4th.
— Review the Advance Program today.

Electronic Components and Technology Conference (ECTC) 🗓

— Electronics Packaging Society’s Flagship Conference …

Dates: May 29 – June 1, 2018
Location: Sheraton Hotel, San Diego, CA USA
Summary: The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange.
— Information and Registration: www.ectc.net
— Save $100 through May 3rd.
— Download the Advance Program today.

Heterogeneous Integration Roadmap Symposium 🗓 🗺

— end of CMOS scaling, difficult challenges, potential solutions, future vision, research, academia, labs, collaboration …

register
Date: Thursday, February 22, 2018
Time: 8:30 AM to 6:00 PM
Cost: $40 IEEE members. students, unemployed, $50 non-members ($10 more, after Feb. 9th)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1802symp-eps.eventbrite.com

Program Outline:
Download Full Program, Hotel Recommendations
— Presentations from HIR Technical Working Group chairs
— Overview from HIR International Roadmap Committee
Sponsors: 
       
We thank our financial supporters:
 
 
 



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.

We firmly believe that the Heterogeneous Integration Roadmap, founded with initiative from the three IEEE Societies — EPS, EDS & Photonics — and in collaboration with SEMI & ASME’s EPPD, has expanded to embrace innovations wherever they arise and promote collaboration wherever possible to accelerate progress in this disruptive digital landscape. Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity and assembled a group of leading technical experts to develop the Roadmap. The first work product of the Roadmap team will be presented by the chairs of the 20 Technical Working Groups for review and feedback.

Plenary Talk: “Synergistic Growth of AI and Silicon Age 4.0 through Heterogeneous Integration of Technologies” — Dr. Nicky Lu, Chairman, CEO & Founder, Etron Technology, Inc., and Managing Board Director, Taiwan Semiconductor Industry Association (TSIA)

Closing Remarks — Dr. Gaurang N. Choksi, Intel: Vice President, Technology and Manufacturing Group; Director, Assembly and Test Technology Development Core Competencies

Program Agenda
8:30: Registration and refreshments
9:00: Start of Program
Download Full Program, with topics, speakers
5:30 – 6:00 pm Wrap-Up

Roadmap Working Groups:
HI for Market Applications
• Mobile
• IoT
• Medical and Health & Wearables
• Automotive
• High Performance Computing and Data Center
• Aerospace and Defense
Heterogeneous Integration Components
• Single-Chip and Multi-Chip Packaging (including Substrates)
• Integrated Photonics
• Integrated Power Electronics
• MEMS & Sensor Integration
• RF and Analog Mixed-Signal Design
• Co-Design and Simulation – Tools & Practice
Cross Cutting topics
• Materials & Emerging Research Materials
• Emerging Research Devices
• Interconnect
• Test
• Supply Chain
• Security (Cyber)
Integration Processes
• SiP
• 3D +2.5D
• WLP (fan in and fan out)

Bio: As a researcher, design architect, entrepreneur and chief executive, Dr. Nicky Lu has dedicated his career to the worldwide IC design and semiconductor industry. He also co-founded several other high-tech companies including Ardentec, Global Unichip and GTBF Corporations. Dr. Lu worked for the IBM Research Division and then the Headquarters from 1982 to 1990 and won numerous IBM recognition awards, including an IBM Corporate Award. He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs over hundreds of billions dollars. Dr. Lu designed several High-Speed CMOS DRAM (HSDRAM) chips, with all top worlds’ records of performance. He was a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan semiconductor industry in early 1990s, also created many Taiwan companies as prominent silicon-chip suppliers. Since 1999 he has pioneered Known-Good-Die Memory Products enabling 3D stacked-dices system chips; this work summoned the new rise of an IC Heterogeneous Integration Era as described in his ISSCC-2004 plenary talk, demonstrating a new 3D-IC trend. He was a keynote speaker at the 2016 A-SSCC disclosing Silicon-Age-4.0 Era with a new Virtual Moore’s Law as a indicator of continual economic growth.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 30 U.S. patents and has published more than 60 technical papers. He serves as Managing Board Director and was Chairman of TSIA, as Board Member of Global Semiconductor Alliance (GSA) and GSA’s General Chair (2009 to 2011), and Chairman of WSC (World Semiconductor Council) from 2014 to 2015. He received the Scientific Management Award (2012) from Chinese Society for Management of Technology and Taiwan’s Golden Merchant Award (2007) from General Chamber of Commerce. He is an Outstanding Alumnus of National Taiwan University, a Chair Professor and an Outstanding Alumnus of National Chiao Tung University, an IEEE Fellow, the recipient of the IEEE 1998 Solid-States Circuits Award, a member of NAE (National Academy of Engineering of USA), and recipient of a SEMI Industry Contribution Award in 2017.


Bio: William (Bill) Chen currently holds the position of ASE Fellow and Senior Technical Advisor at ASE Group. Prior to joining ASE, he was the Director at the Institute of Materials Research & Engineering in Singapore. Bill retired from IBM Corporation after a career spanning over thirty years in various R&D and managerial positions. He has held adjunct and visiting faculty positions at Cornell University, Hong Kong University of Science and Technology, and Binghamton University. Bill is the chair of the newly formed Heterogeneous Integration Technology Roadmap for Semiconductors, an initiative addressing technologies for the IoT/IoE/cloud computing era, jointly sponsored by IEEE EPS, EDS, Photonics Societies, ASME’s EPPD, and SEMI. He also chairs SEMI’s Advanced Packaging Committee. In 2009, Bill received the InterPACK Excellence Award for his contributions, and in 2010, he was presented with the IEEE EPS Society David Feldman Outstanding Contribution Award. He is a past President of the IEEE EPS Society and he has been elected a Fellow of IEEE and a Fellow of ASME. Bill received his B. Sc. from London University, M.Sc. from Brown University and Ph.D. from Cornell University.


Bio: Dr. W. R. “Bill” Bottoms, the holder of a Ph.D. from Tulane University, has an extensive background in academia, venture funding, and in the commercial semiconductor equipment sector. Since founding 3MTS in 1999, Bill Bottoms has provided strategic leadership and vision in keeping with the promise of the 3MTS business model. Dr. Bottoms has also served on a number of important government and industry committees and advisory positions. Key posts include chairmanship of the subcommittee of the Technical Advisory Committee of the United States Commerce Department’s Export Control Commission for Semiconductor Equipment and Materials.
Shortly after receiving his doctorate in physics, Dr. Bottoms joined the electrical engineering faculty of Princeton University, where he remained until 1976. He then joined Varian Associates in Palo Alto, as manager of research and development, and he was later named president of Varian’s newly formed semiconductor equipment group. After leaving Varian, he was senior vice president and general partner at Patricof & Co. Ventures, Inc., an international venture capital firm. He founded Third Millennium Test Solutions in March 1999.