InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) 🗓

— the Electronics Packaging Society’s Key Thermal Conference …

Dates: May 31 – June 3, 2016
Location: Sheraton Hotel, San Diego, CA USA
Summary: The international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems.
— Information and Registration:
— Save $100 through May 4th.
— Review the Advance Program today.

Electronic Components and Technology Conference (ECTC) 🗓

— Electronics Packaging Society’s Flagship Conference …

Dates: May 29 – June 1, 2018
Location: Sheraton Hotel, San Diego, CA USA
Summary: The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange.
— Information and Registration:
— Save $100 through May 3rd.
— Download the Advance Program today.

Heterogeneous Integration Roadmap Symposium 🗓 🗺

— end of CMOS scaling, difficult challenges, potential solutions, future vision, research, academia, labs, collaboration …

Date: Thursday, February 22, 2018
Time: 8:30 AM to 6:00 PM
Cost: $40 IEEE members. students, unemployed, $50 non-members ($10 more, after Feb. 9th)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara

Program Outline:
Download Full Program, Hotel Recommendations
— Presentations from HIR Technical Working Group chairs
— Overview from HIR International Roadmap Committee
We thank our financial supporters:

Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.

We firmly believe that the Heterogeneous Integration Roadmap, founded with initiative from the three IEEE Societies — EPS, EDS & Photonics — and in collaboration with SEMI & ASME’s EPPD, has expanded to embrace innovations wherever they arise and promote collaboration wherever possible to accelerate progress in this disruptive digital landscape. Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity and assembled a group of leading technical experts to develop the Roadmap. The first work product of the Roadmap team will be presented by the chairs of the 20 Technical Working Groups for review and feedback.

Plenary Talk: “Synergistic Growth of AI and Silicon Age 4.0 through Heterogeneous Integration of Technologies” — Dr. Nicky Lu, Chairman, CEO & Founder, Etron Technology, Inc., and Managing Board Director, Taiwan Semiconductor Industry Association (TSIA)

Closing Remarks — Dr. Gaurang N. Choksi, Intel: Vice President, Technology and Manufacturing Group; Director, Assembly and Test Technology Development Core Competencies

Program Agenda
8:30: Registration and refreshments
9:00: Start of Program
Download Full Program, with topics, speakers
5:30 – 6:00 pm Wrap-Up

Roadmap Working Groups:
HI for Market Applications
• Mobile
• IoT
• Medical and Health & Wearables
• Automotive
• High Performance Computing and Data Center
• Aerospace and Defense
Heterogeneous Integration Components
• Single-Chip and Multi-Chip Packaging (including Substrates)
• Integrated Photonics
• Integrated Power Electronics
• MEMS & Sensor Integration
• RF and Analog Mixed-Signal Design
• Co-Design and Simulation – Tools & Practice
Cross Cutting topics
• Materials & Emerging Research Materials
• Emerging Research Devices
• Interconnect
• Test
• Supply Chain
• Security (Cyber)
Integration Processes
• SiP
• 3D +2.5D
• WLP (fan in and fan out)

Bio: As a researcher, design architect, entrepreneur and chief executive, Dr. Nicky Lu has dedicated his career to the worldwide IC design and semiconductor industry. He also co-founded several other high-tech companies including Ardentec, Global Unichip and GTBF Corporations. Dr. Lu worked for the IBM Research Division and then the Headquarters from 1982 to 1990 and won numerous IBM recognition awards, including an IBM Corporate Award. He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs over hundreds of billions dollars. Dr. Lu designed several High-Speed CMOS DRAM (HSDRAM) chips, with all top worlds’ records of performance. He was a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan semiconductor industry in early 1990s, also created many Taiwan companies as prominent silicon-chip suppliers. Since 1999 he has pioneered Known-Good-Die Memory Products enabling 3D stacked-dices system chips; this work summoned the new rise of an IC Heterogeneous Integration Era as described in his ISSCC-2004 plenary talk, demonstrating a new 3D-IC trend. He was a keynote speaker at the 2016 A-SSCC disclosing Silicon-Age-4.0 Era with a new Virtual Moore’s Law as a indicator of continual economic growth.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 30 U.S. patents and has published more than 60 technical papers. He serves as Managing Board Director and was Chairman of TSIA, as Board Member of Global Semiconductor Alliance (GSA) and GSA’s General Chair (2009 to 2011), and Chairman of WSC (World Semiconductor Council) from 2014 to 2015. He received the Scientific Management Award (2012) from Chinese Society for Management of Technology and Taiwan’s Golden Merchant Award (2007) from General Chamber of Commerce. He is an Outstanding Alumnus of National Taiwan University, a Chair Professor and an Outstanding Alumnus of National Chiao Tung University, an IEEE Fellow, the recipient of the IEEE 1998 Solid-States Circuits Award, a member of NAE (National Academy of Engineering of USA), and recipient of a SEMI Industry Contribution Award in 2017.

Bio: William (Bill) Chen currently holds the position of ASE Fellow and Senior Technical Advisor at ASE Group. Prior to joining ASE, he was the Director at the Institute of Materials Research & Engineering in Singapore. Bill retired from IBM Corporation after a career spanning over thirty years in various R&D and managerial positions. He has held adjunct and visiting faculty positions at Cornell University, Hong Kong University of Science and Technology, and Binghamton University. Bill is the chair of the newly formed Heterogeneous Integration Technology Roadmap for Semiconductors, an initiative addressing technologies for the IoT/IoE/cloud computing era, jointly sponsored by IEEE EPS, EDS, Photonics Societies, ASME’s EPPD, and SEMI. He also chairs SEMI’s Advanced Packaging Committee. In 2009, Bill received the InterPACK Excellence Award for his contributions, and in 2010, he was presented with the IEEE EPS Society David Feldman Outstanding Contribution Award. He is a past President of the IEEE EPS Society and he has been elected a Fellow of IEEE and a Fellow of ASME. Bill received his B. Sc. from London University, M.Sc. from Brown University and Ph.D. from Cornell University.

Bio: Dr. W. R. “Bill” Bottoms, the holder of a Ph.D. from Tulane University, has an extensive background in academia, venture funding, and in the commercial semiconductor equipment sector. Since founding 3MTS in 1999, Bill Bottoms has provided strategic leadership and vision in keeping with the promise of the 3MTS business model. Dr. Bottoms has also served on a number of important government and industry committees and advisory positions. Key posts include chairmanship of the subcommittee of the Technical Advisory Committee of the United States Commerce Department’s Export Control Commission for Semiconductor Equipment and Materials.
Shortly after receiving his doctorate in physics, Dr. Bottoms joined the electrical engineering faculty of Princeton University, where he remained until 1976. He then joined Varian Associates in Palo Alto, as manager of research and development, and he was later named president of Varian’s newly formed semiconductor equipment group. After leaving Varian, he was senior vice president and general partner at Patricof & Co. Ventures, Inc., an international venture capital firm. He founded Third Millennium Test Solutions in March 1999.

9th Annual Soft Error Rate (SER) Workshop – Details

Below are summaries of each of the tutorials and talks. Return to this page following the Workshop to download PDFs of the slides.

Presenter Title Details
8:00 AM (PT) On-Site Registration — Coffee, tea
8:30 AM (PT) Introduction to the Workshop
Austin Lesea, Xilinx Tutorial: Single Event Effects (30 minutes) This tutorial is a technical backgrounder on Single Event Effects (SEE) in semiconductor devices, to establish a baseline understanding of origins, effects, mitigation, and testing. Key points made in this presentation are:

  • SEE have a relatively long history and can affect all semiconductor devices.
  • SEE arise from environmental radiation and present a variety of undesired behaviors.
  • SEE mitigation is possible and SEE susceptibility can be measured.

    After this tutorial, attendees will have general familiarity with radiation effects in semiconductor devices. With this background, they will be primed for the other talks which follow.
  • Gary Swift, Swift Engineering Tutorial: Probability and Statistics for Experimenters (30 minutes) This tutorial is a backgrounder on probability and statistics for SEE experiments. SEE experiments are all about counting, which is easy — but understanding counting statistics is important for planning experiments, analyzing measured data, and interpreting the results. Even if you have no plan to run your own experiments, correctly interpreting the work of others is a cornerstone of applying data to make informed decisions in the design of reliable systems.
    Hirotaka Hirano, Mitsubishi Materials Study of the Alpha Counts from Solder Bump Material at Elevated Temperature and Introduction of Advanced Grade Material (30 minutes) We investigated the impact elevated temperature has on the alpha count for the solder bump materials. As a result, it was revealed that the alpha counts increase at elevated temperature due to the surface diffusion of Po. For this reason, we thought that it is necessary to further reduce the alpha counts of the material in order to satisfy the current product guarantee specifications ( < 0.002 cph/cm2 ) even at elevated temperature. Thus, we successfully developed the advanced grade tin material “HULA grade”. The alpha counts of HULA grade material is very low ( < 0.001 cph/cm2) and never increase at elevated temperature even with aging. In this presentation, we would like to introduce the investigation results and the HULA grade material.
    Paul Muller, IBM Assessment of Alpha Particle Susceptibility of Product Chips Through Accelerated Tests (30 minutes) There are several methods for experimentally assessing the soft error rates (SER) of product chips. If it is not an accelerated test, large numbers of chips are exposed to the naturally occurring cosmic rays for a long period of time ranging from months to years.

    Accelerated tests can be carried out using particle accelerators: highly energetic protons or neutrons emulate the impact caused by naturally occurring cosmic rays, but with a flux several orders of magnitude larger than the naturally occurring flux. In order to run an accelerated test for alpha particle sensitivity, one would typically bring a foil source, like Thorium or Americium, into close vicinity to the chip. But that is only feasible if it is a wire bonded chip. If it is a solder bump flip chip, this is very difficult because the space needed for getting the foil source into close vicinity of the chip is occupied by the solder bumps and the substrate.

    We are showing results from a radioactive underfill experiment with a product chip. In this case, the space between the solder bumps, which is typically filled with an ultra-low underfill compound, is filled with a highly radioactive epoxy material. Acceleration factors of 100,000 and higher over naturally occurring alpha fluxes can be achieved. With that, the mean time between events is only minutes to hours, and the time for obtaining statistically meaningful numbers of events is only days or weeks.
    Jaret Heise, Sanford Underground Research Facility Opportunities at the Sanford Underground Research Facility (30 minutes) Building on rich legacies in both mining and transformational physics research, the Sanford Underground Research Facility (SURF), in South Dakota, has been operating as a dedicated research facility for over 10 years. A brief overview of the facility and the science program will be presented. SURF has significant expansion opportunities, and applications from interested research and testing groups are welcome.
    12:00 Noon – 1:00 PM (PT) Lunch and Exhibits
    Jeff Barton and Eric Crabill, Xilinx An Introduction to Real-Time Testing (30 minutes) This presentation provides an introduction to real time testing — also known as atmospheric testing — an accepted test methodology referenced in the JESD89 specification. Learn about its advantages, what is involved in setting up and maintaining experiments, and operational pitfalls to avoid.
    Norbert Seifert, Intel On the Efficacy of Using Proton Beams for Estimating Neutron-Induced Soft Error Rates (30 minutes) This work investigates the feasibility of using high energy proton beams in lieu of, or to complement, broad energy spectrum neutron beams for accelerated testing of the cosmic component of terrestrial soft error rates (SER). Logic and memory devices manufactured in three recent technologies were tested at various proton facilities and their single event upset cross sections compared to soft error rates measured at the Los Alamos Neutron Science Center (LANSCE). Linear energy transfer and soft error simulations were conducted to understand the limits of using proton beam facilities. Both simulation results and experimental data demonstrate that a good correlation between proton cross-section and LANSCE neutron SER can be established for tested devices and technologies.
    Francis Classe, Cypress New High Energy Neutron Spallation Beam, ChipIr, at Appleton-Reutherford Lab at Oxford (30 minutes) This presentation discusses the correlation of a new high-energy neutron spallation beam, ChipIr, at the Appleton-Reutherford Laboratory in Oxford, England. Both Flash memories and SRAM products were tested at the ChipIr beam, and correlated to LANSCE and TRIUMF beams accordingly. The data indicates that the ChipIr beam produces results approximately 1.3 – 2x compared to that of TRIUMF and LANSCE accordingly, making it a very acceptable choice for high energy neutron studies.
    3:30 PM (PT) Close of Workshop

    SEMICON/West sessions: The Package is the System … and Enabling Advanced Applications 🗓

    — complimentary admission, Expo, CPMT-organized sessions, keynotes, panels …

    Morning Session Speakers: Nan Wang, Director of Technology, Cisco; Mike Seddon, MTS, ON Semiconductor; Tim Lee, Technical Fellow, Boeing; Dan Green, PhD, DARPA.
    Afternoon Session Speakers: Babak Sabi, PhD, Corporate VP, Intel; CP Hung, PhD, Corporate VP, ASE Group; David McCann, VP, GLOBALFOUNDRIES
    Dates: Tuesday, July 11 thru Thursday, July 13 2017; CPMT Sessions on Wednesday, July 12th.
    Times Wednesday: 10:30 AM: “The Package is the System is the Product” (5 talks); 2:00 PM: “Advanced Packaging Technologies Enabling Advanced Applications” (4 talks + panel)
    EXPO Hours: Tues 10 AM – 5 PM; Wed 10 AM – 5 PM; Thurs 10 AM – 4 PM
    Cost: EXPO Pass available at no cost through July 8th (includes the CPMT sessions); other options available.
    Location: Moscone Center, S.F.
    Reservations: by July 8th
    Summary: Log in and register for the EXPO Pass; select the keynotes, talks, sessions, panels, etc, that you’d like to attend. Here are some of the talks:
    — MEMS and Sensors: New Intelligence and New Modalities to Drive Next Growth
    — World of IoT: Devices & Data
    — Material Supply Challenges for Current & Future Leading-edge Devices
    — Big Data In Autonomous Driving
    — The Package is the System is the Product
    — 5G: Advanced Semiconductors and Packaging Technologies
    — Advanced Packaging Opportunities and Challenges
    — Vision, Alignment, and Execution of Foundry/OSAT Partnerships to Meet Customer Requirements
    — … plus many more

    9th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓

    — tutorials, alpha upset, materials selection, process control, case studies …

    Date: Tuesday, November 7, 2017
    Time: 8:30 am – 3:00 pm (PT) (Lunch will be provided)
    Location: Xilinx, 2050 Logic Drive, San Jose CA (Map:
    Attendance: On-site or Remote (WebEx)
    Cost: none
    Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.

    Our annual IEEE Soft Error Rate Workshop will enter its 9th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
    You are now invited to register for this year’s event. We will continue a format piloted last year: We have invited two industry experts in the field to offer tutorials on fundamentals of soft errors, and on experimental approaches.
    Presentations: (all times PT)

    Time (PST) Presenter Title
    8:00 AM Check-in and Registration
    8:30 AM Eric Crabill, Xilinx Introductions
    8:45 AM Austin Lesea, Xilinx Tutorial: Single Event Effects (SEEs) (more)
    9:25 AM Gary Swift, Swift Engineering Tutorial: Probability and Statistics for Experimenters (more)
    10:05 AM Hirotaka Hirano, Mitsubishi Materials Study of the Alpha Counts from Solder Bump Material at Elevated Temperature and Introduction of Advanced Grade Material (more)
    10:45 AM Paul Muller, IBM Assessment of Alpha Particle Susceptibility of Product Chips Through Accelerated Tests (more)
    11:25 AM Jaret Heise, Sanford Underground Research Facility, South Dakota Opportunities at the Sanford Underground Research Facility (more)
    12:00 Noon – 12:50 PM Lunch and Discussions
    12:55 PM Jeff Barton and Eric Crabill, Xilinx An Introduction to Real-Time Testing (more)
    1:35 PM Norbert Seifert, Intel On the Efficacy of Using Proton Beams for Estimating Neutron-Induced Soft Error Rates (more)
    2:15 PM Francis Classe, Cypress Semiconductor New High Energy Neutron Spallation Beam, ChipIr, at Appleton-Reutherford Lab at Oxford (more)
    3:00 PM Close of Workshop

    View last year’s program, and downloadable slides, here:

    Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, November 6th.

    Eric Crabill, Xilinx (Chair)
    Peng Su, Juniper Networks
    Rick Wong, Cisco System, Inc.
    Charlie Slayman, Cisco Systems, Inc.
    Shomir Dighe, Santa Clara Valley CPMT Chapter
    Paul Wesling, Santa Clara Valley CPMT Chapter

    Contact us:

    Developing Technology for Autonomous Vehicles and Electric Cars: The Next Platform 🗓 🗺

    — half-day Workshop: automotive environment, materials, packaging, devices for 5G, LiDAR, RADAR …

    (Links to Slides, Below)
    Speakers: Professors and Researchers at Georgia Tech/NSF Packaging Research Center (see below)
    Sponsored by: CPMT Chapter, with Vehicular Technology Chapter, Technology and Engineering Management Chapter, Photonics Chapter
    Workshop Date: Friday, March 24, 2017
    Time: 12:30 PM Registration and Networking; 1:00 – 5:30 PM Workshop; 5:45 Reception
    Cost: $35 IEEE members. students, unemployed, $50 non-members ($15 more at door)

    Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
    For information about exhibiting your technology at this Workshop, please contact Paul Wesling at 408-320-1105.
    Summary: This new era of automotive electronics — such as autonomous driving, in-car smartphone-like infotainment, privacy and security, high-speed and high-bandwidth computing, and all-electric cars — requires an entirely differnt vision than is pursued today. There are unprecedented challenges and opportunities to adress these needs with a systematic approach to system scaling, innovative device and package architectures, and heterogeneous integration for the new era, with particular focus on electrical, mechanical, and thermal designs, and new digital, RF, millimeter wave, LiDAR, camera, high-power and high-temperature electronics technologies.
    The challenges in this new era are many, and include not only new technologies, but also an educated workforce, supply chain manufacturing, roadmaps, and standards. This workshop will describe the needs and challenges, as well as review the state-of-the-art in R&D and in manufacturing.

    Program and Schedule:

    Time Details
    12:30 Registration/Sign-In and Networking
    1:00 The New Era of Automotive Electronics: The Ultimate Electronics System
    Presentation Slides: “The New Era of Automotive Electronics: Intro to GaTech PRC Industry Consortium” (5.2 MB PDF)
    Prof. Rao Tummala, Director, NSF Packaging Research Center
    infotainment, autonomy, innovative architectures, system scaling, design challenges, roadmaps, manufacturing … [more]
    Session 1 Computing and Communications Electronics
    1:45 2.5D Glass Interposer For Ultra-high Bandwidth Computing
    Presentation Slides: “Glass Packaging R&D” (3.2 MB PDF)
    Dr Venky Sundaram and Prof Rao Tummala, Georgia Tech
    — 2.5D and 3D integration, large panel processing, low cost interposers, through-glass vias, reliability, compliant interconnections, data centers … [more]
    2:15 Low- and Medium-Power Electronics
    Presentation Slides: “Power Packaging for Computer Applications” (2 MB PDF)
    Dr. Raj Pulugurtha and Prof Rao Tummala, Georgia Tech
    — IVR, DC-DC converters, substrate-embedded inductors, transformers and capacitors, high-temp and high-voltage capacitors … [more]
    2:45 Coffee, Tea Break; Networking and Exhibitor Interactions
    3:15 5G Communications with Glass Embedding and Fanout
    Presentation Slides: “5G (28-40 GHz) Substrates and Antennas” (.5 MB PDF) and “5G Communications with Glass Embedding and Fanout” (6 MB PDF)
    Prof. Emmanouil Tentzeris, Dr. Venky Sunraram and Dr. Raj Pulugurtha, Georgia Tech
    — Advanced 5G substrates, package-integrated antennas, low-loss and precision 5G transmission lines, passive components … [more]
    Session 2 Sensing Electronics
    3:45 Devices and 3D Glass Fanout Package for Next Generation Radar, Lidar and Camera
    Presentation Slides: “Autonomous Cars: Radar, Lidar, Stereo Cameras” (4 MB PDF)
    Dr. Venky Sundaram, Dr. Chris Valenta, Prof. Peter Hesketh and Prof. John Cressler, Georgia Tech
    — sensor fusion, SiGe devices, low-cost LiDAR packaging, hermetic and near-hermetic glass packages for sensors, design for reliability … [more]
    Session 3 Devices, Packaging and High-Temperature Materials for Power Electronics in Electric Cars
    4:15 High-Power and High-Temperature Electronics for Electric Cars
    Presentation Slides: “High-Power Devices, High-Temperature Materials and Packaging for Electric Cars” (5 MB PDF)
    Prof. Shyh-Chiang Shen, Dr. Vanessa Smet and Dr. Raj Pulugurtha, Georgia Tech
    — Packaging for 150-250 C, high-temp dielectrics and mold compounds, high-temp substrates and fan-out packages … [more]
    Moderator: Paul Wesling
    — Questions, observations, future directions
    Refreshments and Networking
    — snacks and drinks
    — Meet our exhibitors
    — Consult with the speakers
    6:30 Dismissal

    Heterogeneous Integration Roadmap Symposium 🗓

    — 1-day — old ITRS, strategic directions, packaging solutions, SiP, heterogeneous integration, exhibits, reception …

    Symposium Date: Monday, November 14, 2016
    Time: 8:00 AM – 6:30 PM
    Cost: $500 IEEE members, $600 non-members
    Location: Holiday Inn San Jose
    Summary: The IEEE CPMT Society took the initiative to establish a technology roadmap focused on heterogeneous integration, to be modeled after the ITRS in purpose, structure, and governance. This initiative quickly found resonance with SEMI, and the IEEE Electron Devices Society (EDS) joined the effort, resulting in the launch of the Heterogeneous Integration Roadmap (HIR). Please consider attending this first 1-day Symposium with the following sessions:
    MORNING SESSION: Strategic Directions in Heterogeneous Integration
    AFTERNOON SESSION: Innovations in SiP and Integration
    PANEL DISCUSSION: Packaging Solutions to Meet Needs of the Heterogeneous Integration Roadmap
    Reception and Networking: 5:00 PM – 6:30 PM
    SPEAKERS/PANELISTS: Bill Bottoms (3rd Millenium), Bill Chen (ASE), Eelco Bergman (ASE), Tom Coughlin (Coughlin Assoc), Daniel Green (DARPA), Anders Grunnet-Jepsen (Intel), Subramanian Iyer (UCLA), Andrew Kahng (UC-SD), Lionel Kimmerling (MIT), Li Li (Cisco), David McCann (GlobalFoundries), Igino Padovani (Robert Bosch), Gamal Refai-Ahmed (SUNY), Brandon Wang (Cadence).

    Nanotechnology for Energy, Healthcare and the Environment 🗓 🗺

    — half-day Workshop: synthesis, interfaces, markers, nanosheets, biosensors, modeling …

    Presentations: 8 talks plus posters, networking
    Meeting Date: Tuesday, November 15, 2016
    Time: 11:30 AM Registration; 12:15 PM Presentations (through 5:00 PM)
    Cost: $35 for IEEE members; $45 for non-members; $20 for unemployed

    Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
    Reservations:Required, from website
    Information and Registration:

    Summary: The following talks (see website for details):
    — Aerosol Synthesis of Nanomaterials for Hydrogen Generation and Purification Applications (SUNY); — Understanding Structure-Property Relationships for Complex Fluid-Fluid Interfaces (NIST); — Point-of-Care Molecular Detection with Surface Engineering of Nanomaterials for Diagnostic Platforms (U of Toronto); — Microfluidic Platform Technologies for Detection of Biochemical Markers (MIT); — Graphene and Other Nanosheets and processing for nanocomposites and 3D Macrostructures (Texas A&M); — Fast Modeling Protein Corona on Nanoparticle Based Biosensors in Complex Solvent Environments/Cell Membrane by a Coarse Grained Simulation System (U-Mich); — Multiscale Modeling of the Nano-Bio Interface (U-Wisconsin); — DNA Nanotubes Based Adaptive Point-to-Point Assembly (Johns Hopkins Univ).

    Device-Circuit Interaction in Advanced Technology Nodes 🗓 🗺

    — EDS Symposium – deep learning, 5nm node, co-optimization, power circuits, package integration …

    Meeting Date: Friday, November 11, 2016
    Time: 1:00 PM to 5:30 PM
    Cost: $22 for students, $43 for IEEE members, $64 for non-members

    Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
    Summary: This symposium will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes, and consists of talks from five distinguished speakers:
    1. Hardware for Deep Learning, Dr. William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor
    2. Design-Technology Co-Optimization for 5nm Node and Beyond, Dr. Victor Moroz, Scientist, Synopsys
    3. Chip Design and Process Co-optimizations, Design for Manufacturing/Reliability in Advanced Technology Nodes, Dr. John Hu, Director, Advanced Technology, Nvidia Corporation
    4. Process Requirements for Integrated Power Circuits, Dr. Kevin Scoones, Fellow, Texas Instruments
    5. 2.5D/3D Package Integration: Technology Trends, Challenges and Applications, Dr. Suresh Ramalingam, Fellow, Advanced Packaging, Xilinx
    The first talk examines the current state of the art in hardware for deep learning, and highlights the architecture and trends for system-level hardware optimized for artificial intelligence applications. The following talk expands into the device-circuit interactions from finfet devices to devices for the 5nm node and beyond. Standard cell layouts, variability, and performance power area co-optimizations will also be discussed. The 3rd talk focuses on the scaling challenges and process/design interactions, especially circuit and chip level performance, power, density, functionality/yield and reliability co-optimizations. Another important area addressed is power devices and power management, which the 4th talk will focus on, covering the process needs of low voltage power management design and some of the key criteria to enable higher efficiency and lower cost. System-level 3D integration is the next important area to address the system-level scaling requirements. The 5th topic focuses on the key advanced packing enabling technologies for 2.5D/3D and system level integration.