SEMICON/West sessions: The Package is the System … and Enabling Advanced Applications 🗓

— complimentary admission, Expo, CPMT-organized sessions, keynotes, panels …

Morning Session Speakers: Nan Wang, Director of Technology, Cisco; Mike Seddon, MTS, ON Semiconductor; Tim Lee, Technical Fellow, Boeing; Dan Green, PhD, DARPA.
Afternoon Session Speakers: Babak Sabi, PhD, Corporate VP, Intel; CP Hung, PhD, Corporate VP, ASE Group; David McCann, VP, GLOBALFOUNDRIES
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Dates: Tuesday, July 11 thru Thursday, July 13 2017; CPMT Sessions on Wednesday, July 12th.
Times Wednesday: 10:30 AM: “The Package is the System is the Product” (5 talks); 2:00 PM: “Advanced Packaging Technologies Enabling Advanced Applications” (4 talks + panel)
EXPO Hours: Tues 10 AM – 5 PM; Wed 10 AM – 5 PM; Thurs 10 AM – 4 PM
Cost: EXPO Pass available at no cost through July 8th (includes the CPMT sessions); other options available.
Location: Moscone Center, S.F.
Reservations: www.xpressreg.net/register/semi0717/start.asp?sc=IEEE17EXT by July 8th
Summary: Log in and register for the EXPO Pass; select the keynotes, talks, sessions, panels, etc, that you’d like to attend. Here are some of the talks:
— MEMS and Sensors: New Intelligence and New Modalities to Drive Next Growth
— World of IoT: Devices & Data
— Material Supply Challenges for Current & Future Leading-edge Devices
— Big Data In Autonomous Driving
— The Package is the System is the Product
— 5G: Advanced Semiconductors and Packaging Technologies
— Advanced Packaging Opportunities and Challenges
— Vision, Alignment, and Execution of Foundry/OSAT Partnerships to Meet Customer Requirements
— … plus many more

9th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓

— CALL FOR PAPERS: tutorials, alpha upset, materials selection, process control, case studies …

CALL FOR PAPERS (details below)

register
Date: Tuesday, November 7, 2017
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Cost: Free
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Xilinx; Juniper Networks; Cisco Systems.

Our annual IEEE Soft Error Rate Workshop will enter its 9th year!
With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue a format piloted last year: We will be inviting industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
Topics of interest include, but are not limited to:
— Impact of SER on applications including automotive, medical, industrial, and communications
— Advanced silicon nodes and device SER performance assessment
— Techniques and approaches for alpha emissivity measurement
— Success stories of alpha emission or soft error control
— Wafer and assembly process control and monitor
Each talk will be limited to 35 minutes, with additional 5 minutes for questions. The final presentation will be required one week before the event, and will be made available for download after the event. Although new content is especially appreciated, adaptation of content recently published elsewhere is welcome.

ABSTRACT SUBMISSION
Please submit your abstract or proposal at this location

View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations

Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, November 6th.

Please return during October for a listing of tutorials and technical presentations scheduled for the 2017 Soft Error Rate Workshop.

Organizers:
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Cisco System, Inc.
Charlie Slayman, Cisco Systems, Inc.
Shomir Dighe, Santa Clara Valley CPMT Chapter
Paul Wesling, Santa Clara Valley CPMT Chapter

Contact us:

Developing Technology for Autonomous Vehicles and Electric Cars: The Next Platform 🗓 🗺

— half-day Workshop: automotive environment, materials, packaging, devices for 5G, LiDAR, RADAR …

(Links to Slides, Below)
Speakers: Professors and Researchers at Georgia Tech/NSF Packaging Research Center (see below)
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Sponsored by: CPMT Chapter, with Vehicular Technology Chapter, Technology and Engineering Management Chapter, Photonics Chapter
Workshop Date: Friday, March 24, 2017
Time: 12:30 PM Registration and Networking; 1:00 – 5:30 PM Workshop; 5:45 Reception
Cost: $35 IEEE members. students, unemployed, $50 non-members ($15 more at door)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1703cpmt.eventbrite.com
For information about exhibiting your technology at this Workshop, please contact Paul Wesling at 408-320-1105.
Summary: This new era of automotive electronics — such as autonomous driving, in-car smartphone-like infotainment, privacy and security, high-speed and high-bandwidth computing, and all-electric cars — requires an entirely differnt vision than is pursued today. There are unprecedented challenges and opportunities to adress these needs with a systematic approach to system scaling, innovative device and package architectures, and heterogeneous integration for the new era, with particular focus on electrical, mechanical, and thermal designs, and new digital, RF, millimeter wave, LiDAR, camera, high-power and high-temperature electronics technologies.
The challenges in this new era are many, and include not only new technologies, but also an educated workforce, supply chain manufacturing, roadmaps, and standards. This workshop will describe the needs and challenges, as well as review the state-of-the-art in R&D and in manufacturing.

Program and Schedule:

Time Details
12:30 Registration/Sign-In and Networking
1:00 The New Era of Automotive Electronics: The Ultimate Electronics System
Presentation Slides: “The New Era of Automotive Electronics: Intro to GaTech PRC Industry Consortium” (5.2 MB PDF)
Prof. Rao Tummala, Director, NSF Packaging Research Center
infotainment, autonomy, innovative architectures, system scaling, design challenges, roadmaps, manufacturing … [more]
Session 1 Computing and Communications Electronics
1:45 2.5D Glass Interposer For Ultra-high Bandwidth Computing
Presentation Slides: “Glass Packaging R&D” (3.2 MB PDF)
Dr Venky Sundaram and Prof Rao Tummala, Georgia Tech
— 2.5D and 3D integration, large panel processing, low cost interposers, through-glass vias, reliability, compliant interconnections, data centers … [more]
2:15 Low- and Medium-Power Electronics
Presentation Slides: “Power Packaging for Computer Applications” (2 MB PDF)
Dr. Raj Pulugurtha and Prof Rao Tummala, Georgia Tech
— IVR, DC-DC converters, substrate-embedded inductors, transformers and capacitors, high-temp and high-voltage capacitors … [more]
2:45 Coffee, Tea Break; Networking and Exhibitor Interactions
3:15 5G Communications with Glass Embedding and Fanout
Presentation Slides: “5G (28-40 GHz) Substrates and Antennas” (.5 MB PDF) and “5G Communications with Glass Embedding and Fanout” (6 MB PDF)
Prof. Emmanouil Tentzeris, Dr. Venky Sunraram and Dr. Raj Pulugurtha, Georgia Tech
— Advanced 5G substrates, package-integrated antennas, low-loss and precision 5G transmission lines, passive components … [more]
Session 2 Sensing Electronics
3:45 Devices and 3D Glass Fanout Package for Next Generation Radar, Lidar and Camera
Presentation Slides: “Autonomous Cars: Radar, Lidar, Stereo Cameras” (4 MB PDF)
Dr. Venky Sundaram, Dr. Chris Valenta, Prof. Peter Hesketh and Prof. John Cressler, Georgia Tech
— sensor fusion, SiGe devices, low-cost LiDAR packaging, hermetic and near-hermetic glass packages for sensors, design for reliability … [more]
Session 3 Devices, Packaging and High-Temperature Materials for Power Electronics in Electric Cars
4:15 High-Power and High-Temperature Electronics for Electric Cars
Presentation Slides: “High-Power Devices, High-Temperature Materials and Packaging for Electric Cars” (5 MB PDF)
Prof. Shyh-Chiang Shen, Dr. Vanessa Smet and Dr. Raj Pulugurtha, Georgia Tech
— Packaging for 150-250 C, high-temp dielectrics and mold compounds, high-temp substrates and fan-out packages … [more]
5:00
Experts
Panel
Moderator: Paul Wesling
— Questions, observations, future directions
5:45
Reception
Refreshments and Networking
— snacks and drinks
— Meet our exhibitors
— Consult with the speakers
6:30 Dismissal

Heterogeneous Integration Roadmap Symposium 🗓

— 1-day — old ITRS, strategic directions, packaging solutions, SiP, heterogeneous integration, exhibits, reception …

register
Symposium Date: Monday, November 14, 2016
Time: 8:00 AM – 6:30 PM
Cost: $500 IEEE members, $600 non-members
Location: Holiday Inn San Jose
Reservations: www.meptec.org/roadmaps
Summary: The IEEE CPMT Society took the initiative to establish a technology roadmap focused on heterogeneous integration, to be modeled after the ITRS in purpose, structure, and governance. This initiative quickly found resonance with SEMI, and the IEEE Electron Devices Society (EDS) joined the effort, resulting in the launch of the Heterogeneous Integration Roadmap (HIR). Please consider attending this first 1-day Symposium with the following sessions:
MORNING SESSION: Strategic Directions in Heterogeneous Integration
AFTERNOON SESSION: Innovations in SiP and Integration
PANEL DISCUSSION: Packaging Solutions to Meet Needs of the Heterogeneous Integration Roadmap
Reception and Networking: 5:00 PM – 6:30 PM
SPEAKERS/PANELISTS: Bill Bottoms (3rd Millenium), Bill Chen (ASE), Eelco Bergman (ASE), Tom Coughlin (Coughlin Assoc), Daniel Green (DARPA), Anders Grunnet-Jepsen (Intel), Subramanian Iyer (UCLA), Andrew Kahng (UC-SD), Lionel Kimmerling (MIT), Li Li (Cisco), David McCann (GlobalFoundries), Igino Padovani (Robert Bosch), Gamal Refai-Ahmed (SUNY), Brandon Wang (Cadence).

Nanotechnology for Energy, Healthcare and the Environment 🗓 🗺

— half-day Workshop: synthesis, interfaces, markers, nanosheets, biosensors, modeling …

Presentations: 8 talks plus posters, networking
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Meeting Date: Tuesday, November 15, 2016
Time: 11:30 AM Registration; 12:15 PM Presentations (through 5:00 PM)
Cost: $35 for IEEE members; $45 for non-members; $20 for unemployed

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations:Required, from website
Information and Registration: www.ieee.org/nano

Summary: The following talks (see website for details):
— Aerosol Synthesis of Nanomaterials for Hydrogen Generation and Purification Applications (SUNY); — Understanding Structure-Property Relationships for Complex Fluid-Fluid Interfaces (NIST); — Point-of-Care Molecular Detection with Surface Engineering of Nanomaterials for Diagnostic Platforms (U of Toronto); — Microfluidic Platform Technologies for Detection of Biochemical Markers (MIT); — Graphene and Other Nanosheets and processing for nanocomposites and 3D Macrostructures (Texas A&M); — Fast Modeling Protein Corona on Nanoparticle Based Biosensors in Complex Solvent Environments/Cell Membrane by a Coarse Grained Simulation System (U-Mich); — Multiscale Modeling of the Nano-Bio Interface (U-Wisconsin); — DNA Nanotubes Based Adaptive Point-to-Point Assembly (Johns Hopkins Univ).

Device-Circuit Interaction in Advanced Technology Nodes 🗓 🗺

— EDS Symposium – deep learning, 5nm node, co-optimization, power circuits, package integration …

register
Meeting Date: Friday, November 11, 2016
Time: 1:00 PM to 5:30 PM
Cost: $22 for students, $43 for IEEE members, $64 for non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-eds
Summary: This symposium will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes, and consists of talks from five distinguished speakers:
1. Hardware for Deep Learning, Dr. William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor
2. Design-Technology Co-Optimization for 5nm Node and Beyond, Dr. Victor Moroz, Scientist, Synopsys
3. Chip Design and Process Co-optimizations, Design for Manufacturing/Reliability in Advanced Technology Nodes, Dr. John Hu, Director, Advanced Technology, Nvidia Corporation
4. Process Requirements for Integrated Power Circuits, Dr. Kevin Scoones, Fellow, Texas Instruments
5. 2.5D/3D Package Integration: Technology Trends, Challenges and Applications, Dr. Suresh Ramalingam, Fellow, Advanced Packaging, Xilinx
The first talk examines the current state of the art in hardware for deep learning, and highlights the architecture and trends for system-level hardware optimized for artificial intelligence applications. The following talk expands into the device-circuit interactions from finfet devices to devices for the 5nm node and beyond. Standard cell layouts, variability, and performance power area co-optimizations will also be discussed. The 3rd talk focuses on the scaling challenges and process/design interactions, especially circuit and chip level performance, power, density, functionality/yield and reliability co-optimizations. Another important area addressed is power devices and power management, which the 4th talk will focus on, covering the process needs of low voltage power management design and some of the key criteria to enable higher efficiency and lower cost. System-level 3D integration is the next important area to address the system-level scaling requirements. The 5th topic focuses on the key advanced packing enabling technologies for 2.5D/3D and system level integration.

8th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓 🗺

— tutorials, alpha upset, materials selection, process control, case studies …

register
Date: Thursday, November 3, 2016
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Juniper Networks, Building 6, 1215 Borregas Ave, Sunnyvale
Attendance: On-site or Remote (WebEx)
Cost: Free
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Juniper Networks; Pure Technologies; Cisco Systems; XIA.

Our annual IEEE Soft Error Rate Workshop, now in its 8th year, focuses on alpha-induced soft errors with its unique offering of simultaneous on-site and remote participation. It provides opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
This year’s event has a new format: We will be inviting industry experts in the field to offer three tutorials on fundamentals of alpha-related soft errors (shown in red below), to bring engineers and managers up to speed, interspersed with three presentations on current issues, solutions and case studies. Note that all times are Pacific Standard Time; please convert, for your location.
For those participating via WebEx on the Internet, we will send log-in information to all registrants on Wednesday, November 2nd.
See summaries of the contents of the tutorials and talks at this location.

Summary

Time (PST) Presenter Title
9:30 AM Check-in and Registration
10:00 AM Eric Crabill, Xilinx Tutorial: An Introduction to Single Event Effects (more)
10:45 AM Adrian Evans, iROC Tutorial: System Design Considerations for Soft Error Mitigation (more)
11:30 AM Rick Wong, Cisco Challenges of Alpha Testing (more)
12:00 Noon Lunch and Exhibits
1:00 PM Brendan McNelly, XIA; Mike Gordon, IBM Tutorial: Techniques and Challenges of Alpha Emissivity Measurements (more)
1:45 PM Laura Monroe, Los Alamos National Lab Resilience and Inexact Computing (more)
2:15 PM Francis Classe, Cypress Soft Error Upset Sensitivity to the Array Background Pattern in SLC Floating Gate and Charge Trapping Flash Memories (more)
2:45 PM Eric Crabill, Xilinx Alpha-Induced Soft Errors in Xilinx UltraScale+ Devices – Not a ‘Material’ Issue (more)
3:30 PM Close of Workshop

Workshop & Tabletop Expo: Flexible Hybrid Electronics — Opportunities and Challenges 🗓 🗺

Chapter Workshop (with the Consumer Electronics Chapter)

IEEE Santa Clara Valley CPMT Society Chapter Workshop (with the Consumer Electronics Chapter)
Speakers: see below
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Organizers: Shomir Dighe, Chair; Annette Teng, Azmat Malik, Ralic Lo.
Workshop Date: Wednesday, September 21, 2016

  • Registration and continental breakfast: 8:00 AM
  • Call to Order and Welcome: 8:50 AM
  • First presentation: 9:00 AM
  • Lunch, demonstrations: 12:00 PM – 1:00 PM
  • Afternoon presentations: 1:00 PM – 3:30 PM
  • Reception/Networking: 3:30 PM – 4:15 PM
  • Closing: 4:30 PM

Cost: $45 IEEE members; $55 non-members; $25 students, unemployed


Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1609wcpmt.eventbrite.com

Summary:The Workshop is targeted for engineers and managers contemplating entry into the Flexible Hybrid Electronics/Wearables market. It covers the challenges and opportunities in this emerging market. Development trends in the basic building blocks for products in this market will be covered. Experts will provide an overview of polymers, interconnects, sensors and energy sources along with producibility challenges for commercialization.
As a bonus, the workshop will feature product demos and an enlightening market survey followed by a raffle and a networking reception.
Expo: Representatives from a cross section of the Flexible Hybrid Electronics ecosystem as well as the platform developer community will be at tabletop expo that will be open during breaks and lunch.

Speakers:
Opening address/Overview: 9:00 AM (Malcolm Thompson, Executive Director, Next Flex)
9:30 AM: Polymers — Status and Future Developments (to be announced)
10:00 AM: Interconnects — Status and Future Developments (Janos Veres, Program Mgr for Printed Electronics, PARC)
10:40 AM: Flexible TFTs and Flexible Sensors (Arvind Kamath, VP-Technology Development, ThinFilm)
11:00 AM: Power Considerations Including Energy Harvesting (Brian Zahnstecher, PowerROX)
11:30 AM: Flexible Hybrid Electronics Circuit Design and Design Automation (Jim Huang, Research Scientist, HP Labs)
12:00 Noon: Lunch Break & Expo
1:00 PM: Manufacturing Challenges and Opportunities (Dan Gamota, VP-Strategic Capabilities Engng & Tech, Jabil)
1:30 PM: Flexible Display Electronics/Wearables Market (Sweta Dash, President, Dash-Insights)
2:15 PM: Product Demos (including live demo of Fuji Dimatix printer)
3:15 PM: Wrap up and Raffle Drawing
3:30 PM: Reception and Networking

IEEE Electronic Components and Technology Conference 🗓 🗺

— CPMT Society’s Flagship Conference …

— CPMT Society’s Flagship Conference …
Dates: May 31 – June 3, 2016
Location: Cosmopolitan Hotel, Las Vegas, NV
Summary: The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange.
— Information and Registration: www.ectc.net
— Save $100 through May 5th.
— Download the Advance Program today.

IEEE InterSociety Thermal Conference 🗓 🗺

— CPMT Society’s Key Thermal Conference …

— CPMT Society’s Key Thermal Conference …
Dates: May 31 – June 3, 2016
Location: Cosmopolitan Hotel, Las Vegas, NV
Summary: The international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems.
— Information and Registration: www.ieee-itherm.org
— Save $100 through May 5th.
— Download the Advance Program today.