Device-Circuit Interaction in Advanced Technology Nodes 🗓 🗺

— EDS Symposium – deep learning, 5nm node, co-optimization, power circuits, package integration …

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Meeting Date: Friday, November 11, 2016
Time: 1:00 PM to 5:30 PM
Cost: $22 for students, $43 for IEEE members, $64 for non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-eds
Summary: This symposium will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes, and consists of talks from five distinguished speakers:
1. Hardware for Deep Learning, Dr. William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor
2. Design-Technology Co-Optimization for 5nm Node and Beyond, Dr. Victor Moroz, Scientist, Synopsys
3. Chip Design and Process Co-optimizations, Design for Manufacturing/Reliability in Advanced Technology Nodes, Dr. John Hu, Director, Advanced Technology, Nvidia Corporation
4. Process Requirements for Integrated Power Circuits, Dr. Kevin Scoones, Fellow, Texas Instruments
5. 2.5D/3D Package Integration: Technology Trends, Challenges and Applications, Dr. Suresh Ramalingam, Fellow, Advanced Packaging, Xilinx
The first talk examines the current state of the art in hardware for deep learning, and highlights the architecture and trends for system-level hardware optimized for artificial intelligence applications. The following talk expands into the device-circuit interactions from finfet devices to devices for the 5nm node and beyond. Standard cell layouts, variability, and performance power area co-optimizations will also be discussed. The 3rd talk focuses on the scaling challenges and process/design interactions, especially circuit and chip level performance, power, density, functionality/yield and reliability co-optimizations. Another important area addressed is power devices and power management, which the 4th talk will focus on, covering the process needs of low voltage power management design and some of the key criteria to enable higher efficiency and lower cost. System-level 3D integration is the next important area to address the system-level scaling requirements. The 5th topic focuses on the key advanced packing enabling technologies for 2.5D/3D and system level integration.

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