9th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓

— tutorials, alpha upset, materials selection, process control, case studies …

register
Date: Tuesday, November 7, 2017
Time: 8:30 am – 3:00 pm (PT) (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Cost: none
Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.

Our annual IEEE Soft Error Rate Workshop will enter its 9th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
You are now invited to register for this year’s event. We will continue a format piloted last year: We have invited two industry experts in the field to offer tutorials on fundamentals of soft errors, and on experimental approaches.
Presentations: (all times PT)

Time (PST) Presenter Title
8:00 AM Check-in and Registration
8:30 AM Eric Crabill, Xilinx Introductions
8:45 AM Austin Lesea, Xilinx Tutorial: Single Event Effects (SEEs) (more)
9:25 AM Gary Swift, Swift Engineering Tutorial: Probability and Statistics for Experimenters (more)
10:05 AM Hirotaka Hirano, Mitsubishi Materials Study of the Alpha Counts from Solder Bump Material at Elevated Temperature and Introduction of Advanced Grade Material (more)
10:45 AM Paul Muller, IBM Assessment of Alpha Particle Susceptibility of Product Chips Through Accelerated Tests (more)
11:25 AM Jaret Heise, Sanford Underground Research Facility, South Dakota Opportunities at the Sanford Underground Research Facility (more)
12:00 Noon – 12:50 PM Lunch and Discussions
12:55 PM Jeff Barton and Eric Crabill, Xilinx An Introduction to Real-Time Testing (more)
1:35 PM Norbert Seifert, Intel On the Efficacy of Using Proton Beams for Estimating Neutron-Induced Soft Error Rates (more)
2:15 PM Francis Classe, Cypress Semiconductor New High Energy Neutron Spallation Beam, ChipIr, at Appleton-Reutherford Lab at Oxford (more)
3:00 PM Close of Workshop

View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations

Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, November 6th.

Organizers:
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Cisco System, Inc.
Charlie Slayman, Cisco Systems, Inc.
Shomir Dighe, Santa Clara Valley CPMT Chapter
Paul Wesling, Santa Clara Valley CPMT Chapter

Contact us: