CALL FOR PAPERS (details below)
Date: Tuesday, November 7, 2017
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Xilinx; Juniper Networks; Cisco Systems.
Our annual IEEE Soft Error Rate Workshop will enter its 9th year!
With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue a format piloted last year: We will be inviting industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
Topics of interest include, but are not limited to:
— Impact of SER on applications including automotive, medical, industrial, and communications
— Advanced silicon nodes and device SER performance assessment
— Techniques and approaches for alpha emissivity measurement
— Success stories of alpha emission or soft error control
— Wafer and assembly process control and monitor
Each talk will be limited to 35 minutes, with additional 5 minutes for questions. The final presentation will be required one week before the event, and will be made available for download after the event. Although new content is especially appreciated, adaptation of content recently published elsewhere is welcome.
Please submit your abstract or proposal at this location
View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations
Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, November 6th.
Please return during October for a listing of tutorials and technical presentations scheduled for the 2017 Soft Error Rate Workshop.
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Cisco System, Inc.
Charlie Slayman, Cisco Systems, Inc.
Shomir Dighe, Santa Clara Valley CPMT Chapter
Paul Wesling, Santa Clara Valley CPMT Chapter