Speakers: Dr. Chris Bailey, University of Greenwich, and Dr. Jie Xue, Cisco
Meeting Date: Tuesday September 19, 2017
Time: 8:00 AM (PDT)
Cost: none (for CPMT/EP members only)
Location: on the Internet
Summary: 3D-Printing (or Additive Manufacturing) has received significant media attention during the last five years. In 2012 the Economist published an article on this technology which stated that it will lead to a 3rd industrial revolution. A number of companies are now commercializing materials, design/software and 3D-Printers, and these are being used in a number of manufacturing sectors including aerospace, medical, and construction and consumer products. In China alone the 3D-Printer market is expected to be worth over 10Bn RMB by 2018, and the Government has recently initiated a policy to provide every school with 3D-printing capabilities.
But what impact will 3D-printing have on the electronics packaging and manufacturing community? Will 3D-Printing be just hype, or is there hope that these technologies will impact the way we manufacture and package electronic systems — or are developments already being commercialized? Will 3D-Printing of electronic circuits or components be the next phase of the additive manufacturing revolution? This presentation will discuss the challenges for design tools, materials, and 3D-printing processes in the context of electronics manufacturing/packaging. In particular, printing and micro-assembly systems are required that can accurately deposit and cure both functional and structural materials and place/embed components in an integrated manner within a single platform. The performance and electrical behavour of printed conductive materials is also a challenge as they must meet the performance of materials currently used. And of course the overall quality and reliability of 3D-printed electronic systems must meet industry requirements. This presentation will detail the current status of 3D-printing for the manufacture of electronic systems, and provide some insights on how it may impact our community in the future.
Bio: Dr. Jie Xue is currently the Sr. director of the Component Quality and Technology Group at Cisco Systems, Inc., San Jose. Her team is responsible for component technology development and qualification of ASIC, network processors and optical modules, as well as the development of advanced semiconductor and packaging technologies. Since joining Cisco in 2000, she has been working on developing high performance flip chip packaging, system-in-package, multi-chip modules, and chip-scale-packaging for high-reliability networking products. Prior to joining Cisco, Jie held several management and engineering positions in Motorola Inc., working on R&D and product development.
Bio: Dr. Chris Bailey is Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. He received his PhD in Computational Modeling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, he worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.