Date: Wednesday, October 24, 2018 (Talk proposals due Sept 12, 2018)
Time: 9:30 am – 3:00 pm (PT) (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.
Download the Call for Abstracts
Our annual IEEE Soft Error Rate Workshop will enter its 10th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue with the format used in the previous two years: We will be inviting industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications, as well as selected submitted proposals.
View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations
Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, October 22.
Topics of interest include, but are not limited to:
— Impact of soft error rates/mechanisms on commercial/terrestrial applications
— Advanced silicon nodes and device SER performance assessment
— Techniques and approaches for alpha emissivity measurement
— Success stories of alpha emission or soft error control
— Wafer and assembly process control and monitor
Each talk will be limited to 35 minutes, with an additional 5 minutes for questions. The final presentation must be submitted one week before the event, and will be posted as PDF for download after the event. Although new content is especially appreciated, adaptation of content recently published elsewhere is welcome.
The deadline for technical presentations and tutorial abstracts is September 12, 2018. Please email your proposal to Eric Crabill, Xilinx, at email@example.com
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Charlie Slayman, Cisco Systems, Inc.
Shomir Dighe, Paul Wesling, Santa Clara Valley EPS Chapter
Vijay Narasimhan, Jin-woo Han, Santa Clara Valley EDS Chapter
Contact us: 2018 SER Workshop