Date: Wednesday, October 24, 2018
Time: 8:30 am – 4:00 pm (PT) (Lunch will be provided)
Location: Xilinx, 2050 Logic Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.
Our annual IEEE Soft Error Rate Workshop will enter its 10th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue with the format used in the previous two years, with invitied industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
Tutorial: “Single Event Effects”, Eric Crabill, Xilinx
“Multi Bit Upset Mitigation Using the Fall-Off Curve”, Paul Muller, IBM
“Proton Single-Event Upset Characterization of Memory Interface Design on Xilinx XCKU040 FPGA”, Pierre Maillard, Xilinx
“Soft Errors: From Technology Trends to System Level Performance”, Balaji Narasimhan, Broadcom
The Ultra-low Background Radioassay Racilities at the Boulby Underground Laboratory”, Dr. Chamkaur Ghag, University College London
“The Crocker Nuclear Laboratory and Cyclotron”, Eric Prebys, UC Davis
“64 MeV Proton Single-Event Evaluation of Xilinx 20nm DDR4-IO Design”, Paula Chen, Xilinx
“Logic Upsets in DDR4 SDRAM using 480 MeV Proton”, Sang Hoon Jeon, HanYang University
“Making the Grade: From COTS to Space-grade Electronics”, Robert Baumann, Radiosity Solutions
“The Alpha Foil SEU Test Methodology: Clarifying Inherent Problems and Identifying Possible Alternatives”, Gary Swift, Swift Radiation Services
“(Title to be determined)”, Brendan McNally, XIA
“Physics-Inspired Spreadsheet Models for Latch and SRAM SER Screening”, Phil Oldiges, IBM
“Soft Error Rate Measurements in Solid State Drives”, Vinod Ambrose, Intel
… plus another 2 in final stages of acceptance.
View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations
Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, October 22.
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Charlie Slayman, Cisco Systems, Inc.
Shomir Dighe, Paul Wesling, Santa Clara Valley EPS Chapter
Vijay Narasimhan, Jin-woo Han, Santa Clara Valley EDS Chapter
Contact us: 2018 SER Workshop