Date: Wednesday, October 24, 2018
Time: 8:30 am – 4:30 pm (PT) (Lunch will be provided)
Location: Xilinx, 2100 All Programmable Drive, San Jose CA (Map: goo.gl/maps/V7GpFxFH8u72)
Attendance: On-site or Remote (WebEx)
Sponsors: IEEE Santa Clara Valley (SCV) Chapters for Electronics Packaging, Electron Devices, and Reliability; and Xilinx; Juniper Networks; Cisco Systems.
Our annual IEEE Soft Error Rate Workshop will enter its 10th year! With our focus on alpha-induced soft errors and unique offering of simultaneous on-site and remote participation, we have provided opportunities for presentation and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
For this year’s event, we will continue with the format used in the previous two years, with invitied industry experts in the field to offer technical presentations and tutorials on fundamentals of soft errors and their impact on applications.
(All times shown are Pacific Daylight Time, California)
|8:15 AM||Check-in and Registration||WebEx: Login information will be sent to registrants on Monday, October 22.|
|8:35 AM||Paul Muller, IBM||Multi Bit Upset Mitigation Using the Fall Off Curve (more)|
|9:05 AM||Chamkaur Ghag, University College London||Ultra-Low Background Radioassay Facilities at the Boulby Underground Laboratory (more)|
|9:35 AM||Joe Hupcey, Mentor||Exhaustively Verify EDAC Protected State Machines and Memories Using Formal Verification (more)|
|10:15 AM||Paula Chen, Xilinx||64 MeV Proton Single-Event Evaluation of Xilinx 20nm DDR4-IO Design (more)|
|10:45 AM||Sang Hoon Jeon, HanYang University||Logic Upsets in DDR4 SDRAMs Using 480 MeV Protons (more)|
|11:15 AM||Robert Baumann, Radiosity Solutions||Making the Grade: From COTS to Space-grade Electronics (more)|
|12:15 – 12:45 PM||Lunch and Discussions||(Lunch will be provided)||12:45 PM||Eric Prebys, UC Davis||The Crocker Nuclear Laboratory (more)|
|1:15 PM||Mark Hanhardt, Sanford Underground||Research Opportunities at Sanford Underground Research Facility (more)|
|1:45 PM||Krishna Mohan, GlobalFoundries||Demonstration of Soft Error Rate Robustness with Process Improvements and Material Changes – Case Studies (more)|
|2:15 PM||Balaji Narasimhan, Broadcom||Soft Errors: From Technology Trends to System-Level Performance (more)|
|3:00 PM||Y. Sawada, MMC||Development of High-Precision and Sensitive 2? Gas Flow-Type Alpha Particle Counter (more)|
|3:30 PM||Phil Oldiges, IBM||Physics-Inspired Spreadsheet Models for Latch and SRAM SER Screening (more)|
|4:00 PM||Vinod Ambrose, Intel||Soft Error Rate Measurements in Solid State Drives (more)|
|4:30 PM||Close of Workshop|
View last year’s program, and downloadable slides, here: sites.google.com/site/ieeescvserworkshop/Presentations
Note that all times are Pacific Standard Time; please convert, for your location. For those participating via WebEx on the Internet, we will send log-in information to all registrants on Monday, October 22.
Eric Crabill, Xilinx (Chair)
Peng Su, Juniper Networks
Rick Wong, Charlie Slayman, Cisco Systems, Inc.
K. Paul Muller, IBM
Norbert Seifert, Intel
Shomir Dighe, Paul Wesling, Santa Clara Valley EPS Chapter
Vijay Narasimhan, Jin-woo Han, Santa Clara Valley EDS Chapter
Contact us: 2018 SER Workshop