Speaker: Dr. Azita Emami, Professor, California Institute of Technology, and IEEE-SSCS Distinguished Lecturer
Meeting Date: Thursday, December 6, 2018
Time: 6:00 PM Networking and refreshments; 6:30 PM Presentation
Cost: Free, donation is accepted for refreshments: $2 IEEE members/$5 non-members, pay online or at the door
Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: The scalability of CMOS technology has driven computation into a diverse range of applications across the power-consumption, performance and size spectra. Today, Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large-scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular, effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.
Bio: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.