Heterogeneous Integration Roadmap 2-Day Symposium 🗓 🗺

— 2nd Annual, intro to HIR v1.0, overviews, integration, working groups, participation …

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Dates: Thursday, 21 February 2019 (8:30 AM – 6:00 PM) and Friday 22 February (8:30 AM – 4:00 PM)
Cost: $50 General Admission; $35 IEEE/ASME members and employees of SEMI member companies; $35 for students, unemployed, retired.

Location: SEMI International Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 1902symp-eps.eventbrite.com

Program Outline: (details below)
Download Full Program, Hotel Recommendations
NOTE: No photographs or videos will be allowed during the Symposium. (This announcement complies with IEEE policies.)
Day 1: Introduction to HIR v1.0
— Release of HIR version 1.0: How to Download and Use the Roadmap
— Presentations from HIR Technical Working Group chairs
Day 2: TWG Breakout Sessions for HIR v2.0 (TWG Caucus & Cross-TWG meetings)

Sponsors:

We thank our financial supporters for 2019:
     



Summary: We are entering the era of the digital economy and myriad connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress will require a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.

A Heterogeneous Integration Roadmap is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). It will be a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and in fact our own profession.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have developed a broad and inclusive worldview to comprehend this diversity, and assembled a group of leading technical experts to develop this Roadmap. The first work product of the Roadmap team is being presented by the chairs of the 20 Technical Working Groups. This Version 1.0 is now being released, for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, 21 February 2019: Introduction to HIR v1.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00: Start of Program: Welcome – Ajit Manocha, President & CEO, SEMI Int’l
9:15 – 10:50 AM – Session 1 – Heterogeneous Integration for High Performance
                Chair: Bill Bottoms, EPS and 3MTS
    — High Performance Computing & Data Center, Kanad Ghose (Binghamton U), Dale Becker (IBM)
    — 3D and Interconnect, Ravi Mahajan (Intel)
    — Thermal Management, Madhu Iyenger (Google), Azmat Malik (Acuventures)
    — Integrated Photonics, Amr Helmy (U-Toronto), Bill Bottoms (3MTS)
    — WLP (fan-in and fan-out), Rozalia Beica (DOW), John Hunt (ASE)
    — Test, Dave Armstrong (Advantest)
BREAK
11:00 – 12:30 PM – Session 2 – Heterogeneous Integration for Consumer and Industrial Applications
                Chair: Subu Iyer, UCLA
    — Emerging Devices, Meyya Meyyappan (NASA Ames)
    — Medical, Health and Wearables, Mark Poliks (Binghamton U), Nancy Stoffel (GE), Benson Chan (Binghamton U)
    — SiP & Modules, Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon)
    — Single Chip and Multi Chip Integration, William Chen (ASE), Annette Teng (Promex)
    — Integrated Power Packaging, Patrick McClusky (UMD), Doug Hopkins (NCSU)
    — IoT, Robert Lo (ITRI Taiwan)
12:30 PM – Hosts Recognition; Symposium Sponsor Thank You
12:40 – 1:40 PM – LUNCH     (discussions; box lunch included)
1:40 – 2:25 PM – PLENARY PRESENTATION
Invited Speaker: Babak Sabi, Corporate Vice President, General Manager of Assembly & Test Development, Intel Corporation
2:25 – 3:45 PM -Session 3 – Heterogeneous Integration for Special Applications
                Chair: Tom Salmon, SEMI
    — Aerospace and Defense, Tim Lee (Boeing)
    — 5G in RF and Analog Mixed Signal, Tim Lee (Boeing), Herbert Bennett (Alta Tech)
    — Cyber Security, Sohrab Aftabjahani (Intel)
    — Simulation, Richard Rao (Microsemi), Chris Bailey (U-Greenwich), Xuejun Fan (Lamar U)
    — Co-Design, Jose Schutt-Aine (U of Illinois)
    — MEMS and Sensor Integration, Shafi Saiyed (ADI)
BREAK
4:00 – 5:15 PM – Session 4 – Heterogeneous Integration Applications, Materials & Simulation
                Chair: Amr Helmy, Univ of Toronto
    — Automotive, Urmi Ray (STATS ChipPAC), Rich Rice (ASE)
    — Mobile, William Chen (ASE)
    — Materials and Emerging Research Materials, Bill Bottoms (3MTS)
    — Supply Chain, Tom Salmon (SEMI)
5:15 PM – Information on Release of HIR version 1.0; Download & Roadmap Use
5:30 PM – WRAP UP: Nicky Lu, CEO and Chairman, Etron Technology Inc.
5:45 – 6:45 PM Reception, Social
Wine-tasting and sampling many fine wines from Napa Valley with bartender John Friedlund

Friday, 22 February 2019: TWG Breakout Sessions for HIR & Open House v2.0
Who should attend: All HIR Technical Working Group members and anyone interested in participating or learning more about the Heterogeneous Integration Roadmap and participating in interaction, collaboration and feedback.
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30: Registration and refreshments
9:00: HIR Business:     — Completion of manuscript: Full Roadmaps & White Papers     — HIR 1.0 Release plan     — Peer Review     — Chapters Complete     — Download Schedules     — Planning for HIR 2.0     — 2019 Events: ECTC Las Vegas, SEMICON West, Asia, Europe
10:30: Breakout Sessions A and B, TWG Exchange Caucuses
Lunch (box lunches provided)
1:00 PM – Breakout Sessions C and D, TWG Exchange Caucuses
2:30 PM – Wrap-Up

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