Advanced Packaging: A Perspective on 2D and 3D Architectures ๐Ÿ—“ ๐Ÿ—บ

— heterogeneous integration, drivers, evolution, density, options, developments needed, scaling …

Speaker: Dr. Deepak Goyal, Director of the Assembly and Test Technology FA Labs, Intel register
Meeting Date: Thursday, February 7, 2019
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: SEMI World Hdqtrs, 673 South Milpitas Blvd, Milpitas
Summary: Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems. HI is crucially enabled by advanced packaging, since packages are an optimal HI platform. This talk will address the role of advanced packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities. It will show how 2D and 3D packaging has evolved to provide increased interconnect density and how the different technology solutions available today meet the demands of diverse markets. Key high-end technologies such as EMIB, the silicon interposer and Foveros will be discussed in this context. The talk will also touch on the evolving future challenges in interconnect density scaling. In addition to interconnect scaling, this talk will also briefly discuss challenges and opportunities in key areas such as power management, high speed IO, thermal management, test and FI/FA.

Bio: Deepak Goyal graduated with a PhD from State University of New York, Stony Brook, and joined Intel as a Failure Analysis Engineer. He is currently the Director of the Assembly and Test Technology Development Failure Analysis Labs at Intel. His responsibilities include development of the next generation of analytical tools and techniques, defect characterization, fault isolation, failure and materials analyses for the next generation package technology development at Intel, analytical chemistry labs in support of the substrate development and manufacturing, and Board and System level failure analysis. He has helped with the development of all Intel assembly technologies including FCxGA, FCCSP, TSVs, EMIB and Foveros. He is an expert in the failure analysis of packages and has taught Professional Development courses on Package FA/FI methods and failure mechanisms at the Electronics Components and Technology Conference (ECTC) from 2003 to present. He has won two Intel Achievement Awards and 25 Division Recognition Awards at Intel. Deepak has authored and co-authored over 50 papers and holds 11 US patents with 5 more in flight. He has co-authored 2 book chapters and has co-edited a book titled โ€œ3D Microelectronic Packaging: From Fundamentals to Applicationsโ€. He is a senior member of the IEEE and was the chair of the Package and Interconnect Failure Analysis Forum sponsored by International Sematech. He is currently the chair of the ECTC Applied Reliability Committee.

SEMI World Hdqtrs, Milpitas Map