12:00 – 12:30: “Non-Destructive Characterization of Advanced IC Packages with Buried Features using 3D X-ray”
Speaker #1: Thom Gregorich, Carl Zeiss PCS Inc.
12:30 – 1:15: “High Density D2W DBI Hybrid Bonding for 2.5D/3D Applications”
Speaker #2: Dr. Sitaram Arkalgud, Xperi
Meeting Date: Wednesday, April 10, 2019
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM First Presentation; 12:30 PM Second Presentation
Presentations-only: 12:00 noon (come at 11:45 or 12:15)
Cost: $5 IEEE members, students, unemployed; $10 non-members
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
First Talk Summary (Thomas Gregorich): For more than 40 years the semiconductor industry has been driven by silicon scaling: minimum CMOS feature size scaled from tens of microns down to a few nanometers. During the same period, minimum package feature size scaled much less, largely because it was more beneficial to scale the silicon than to scale the package. However, silicon scaling is slowing down and there are other challenges such as memory bandwidth and reliability which cannot be solved by silicon scaling. It is clear that package technology is being pushed out of its “comfort zone” and has entered an era of aggressive feature scaling and performance enhancement.
This presentation will explore the history of feature size scaling in wafer fabrication and the types of inspection and metrology systems which were developed to enable this scaling. Inspection and metrology process flows in wafer fabrication will be compared to inspection and metrology process flows in package assembly, and opportunities will be identified to enhance inspection and metrology systems in package assembly. The ZEISS Xradia Versa 620 X-ray Microscope and Measurement System will be introduced as a non-destructive solution to enhance package inspection and metrology during development and characterization, and several use cases will be presented.
Bio: Mr. Thomas Gregorich is Director of Business Development at ZEISS Semiconductor Manufacturing Technology where he is responsible for imaging products which support Advanced Packaging. Previously Mr. Gregorich held senior-level positions at Western Digital, Micron, Broadcom, MediaTek and Qualcomm. At Micron Mr. Gregorich qualified the Company’s first commercial TSV product. While at Qualcomm he established the Package Engineering department and for 12 years led the development of Qualcomm’s small form-factor package portfolio including NSP, CSP, BCC, QFN, POP and PIP. Prior to his position at Qualcomm, Mr. Gregorich worked for Motorola and had assignments in the Semiconductor Products Sector and Corporate Research, both in the United States as well as Japan, Taiwan and China. Mr. Gregorich has a BS in Mechanical Engineering from Bradley University, an MBA from Northern Illinois University and is a Senior Member of IEEE.
Second Talk Summary (Sitaram Arkalgud): Chip and wafer stacking have made major inroads into several semiconductor segments, including CMOS Image Sensors, MEMS and HPC. As stacking becomes a necessity, it continues to expand into DRAM, RF and other markets. Microbumps are today’s interconnect of choice, but they face issues of scalability and reliability, together with underfill and polyimide layers introducing thermo-mechanical issues which worsen with large dies. This talk describes a room-temperature hybrid bonding process that eliminates microbumps and associated organic layers, resulting in high reliability, low cost, and high density interconnects with improved thermo-mechanical performance. It will present our D2W DBI development work targeting 2.5D and 3D applications.
Bio: Sitaram Arkalgud is driving the application of Xperi bonding technologies (ZiBond® and DBI®) in numerous 3D products across the industry. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Xperi (Invensas), he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, Cu/Cu wafer/die bonding and wafer thinning for 3D ICs. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 45 U.S. patents. Sitaram holds Masters and Ph.D. degrees in Materials Engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a Bachelor’s degree in Metallurgical Engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.