Recent Advances and Outlook for Heterogeneous Integration 🗓 🗺

— integrating dissimilar chips, 2.5 and 3D, various substrates, new processes, time-to-market, cost …

Speaker: John H. Lau, Unimicron Technology Corporation
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Meeting Date: Friday, February 28, 2020
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas
Reservations: 2002eps.eventbrite.com
Summary: Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stacked) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. In the coming years we will see more implementations of higher levels of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the definition, classifications, applications, and trends in heterogeneous integration will be presented. Outline:
— Definition of Heterogeneous Integration
— Classifications of Heterogeneous Integration: on Organic Substrates; on Silicon Substrates (TSV-Interposers); on Silicon Substrates (TSV-less Interposers); on Fan-Out RDL Substrates; on Ceramics Substrates
— Applications of Heterogeneous Integration: of PoP; of CIS and Logic Chips; of LED and TSV-Interposers; of MEMS and Logic Chips; of VCSEL and PD
–Trends in Heterogeneous Integration


Bio: John Lau has more than 39 years of R&D and manufacturing experience in semiconductor packaging, and has published more than 490 peer-reviewed papers, has 30 issued and pending US patents, and 20 textbooks on, e.g., Heterogeneous Integration (Springer 2019). John has been an IEEE Fellow since 1994, and is an IMAPS and ASME Fellow.

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