Heterogeneous Integration Roadmap Annual Meeting & Symposium 🗓 🗺

3nd HIR Annual Meeting, implementation, cross-TWG integration, participation, work on HIR v2.0 …

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Dates: Thursday, 20 February 2020 (8:30 AM – 6:30 PM) and Friday 21 February (8:30 AM – 4:00 PM)
Cost: $60 General Admission; $50 IEEE/ASME members and employees of SEMI member companies; $25 for retired, unemployed, students. ($20 more after 14 February); includes 2 lunches, wine-tasting
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas CA USA
Information and Reservations: 2002symp-eps.eventbrite.com

Program Outline: (details below)
NOTE: No photographs or videos are allowed during the Symposium. (This announcement complies with IEEE policies.)
Day 1: Implementation of HIR v1.0
— Keynotes on Future Implementations and Challenges
— Moderated Panels on Key Aspects of the Released Roadmap
Day 2: TWG Breakout Sessions for HIR v2.0 (TWG Caucus & Cross-TWG meetings)

Event Sponsors:

Summary: We are entering the era of the digital economy and ubiquitous connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into global society, and the plateauing of CMOS’s scaling advantage, continued progress now requires a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
The Heterogeneous Integration Roadmap published in 2019 is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). This is a pre-competitive technology roadmap addressing future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and own professional careers.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have released this new Roadmap — a broad and inclusive worldview to comprehend this diversity, developed by a group of leading technical experts. It was made available in 2019 for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, 20 February 2020: Implementation of HIR v1.0; Work on v2.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00 – 9:35: Start of Program; Welcome by Ajit Manocha, SEMI CEO
9:25 – 9:55: Plenary Speaker: Dr Pradeep Dubey, Intel Senior Fellow & Director, Intel Parallel Computing Lab
10:05 – 11:15 – Session 1 – Heterogeneous Integration for High Performance, Chair: Amr Helmy, Univ of Toronto & IEEE Photonics Society
— 5G, RF and Analog Mixed Signal: Tim Lee (Boeing), Herbert Bennett (Alta Tech)
— Mobile: William Chen (ASE), Benson Chen (Binghamton University)
— Aerospace & Defense: Tim Lee (Boeing), Jeff Demmin (Keysight)
— WLP (Fan-in & Fan-Out): Rozalia Beica (iNEMI), John Hunt (ASE)
— Simulation: Chris Bailey (University of Greenwich), Xuejun Fan (Lamar University)
— Materials & Emerging Research Materials: Bill Bottoms (3MTS)
    — Moderated Panel and Discussion: Representatives of Working Groups
BREAK
11:30 – 12:30 – Session 2 – Heterogeneous Integration for Consumer & Industrial Applications, Chair: Ravi Mahajan, ASME EPPD & Intel
— Medical and Health & Wearables: Mark Poliks (Binghamton U), Nancy Stoffel (GE)
— SiP & Module: Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon), Erik Jung (IZM)
— Single Chip and Multi Chip Integration: William Chen (ASE), Annette Teng (Promex)
— Emerging Research Devices: Meyya Meyyappan (NASA Ames)
— Co-Design: Jose Schutt-Aine (University of Illinois)
    — Moderated Panel and Discussion: Representatives of Working Groups
12:30 – 1:20 – LUNCH     (discussions; box lunch included)
1:20 – 1:50 – Plenary Speaker: Dr. Hong Liu, Distinguished Engineer & Senior Director, Google Technical Infrastructure
1:50 – 2:50 – Session 3 – Heterogeneous Integration for High-Performance Computing, Chair: Bill Bottoms, IEEE EPS & 3MTS
— High Performance Computing & Data Centers: Kanad Ghose (Binghamton University), Dale Becker (IBM), Rockwell Hsu (Cisco)
— 2D-3D & Interconnect: Ravi Mahajan (Intel)
— Thermal Management: Madhu Iyenger (Google), Azmat Malik (Acuventures)
— Integrated Photonics: Amr Helmy (University of Toronto), Bill Bottoms (3MTS)
— Test: David Armstrong (Adventest)
    — Moderated Panel and Discussion: Representatives of Working Groups
BREAK
3:10 – 4:20 – Session 4 – Heterogeneous Integration for Special Applications , Chair: Paul Trio, SEMI
— Automotive: Urmi Ray (iNEMI), Rich Rice (ASE)
— MEMS & Sensor Integration: Shafi Saiyed (ADI)
— Integrated Power Packaging: Patrick McCluskey (U-Md), Doug Hopkins (NCSU)
— Cyber Security: Sohrab Aftabjahani (Intel)
— Supply Chain: Tom Salmon (SEMI)
— IoT: Robert Lo (ITRI)
    — Moderated Panel and Discussion: Representatives of Working Groups
4:20 – 5:20pm -HIR Open Forum: Feedback & Comments
5:20 – 5:45 PM – Wrapup: Next-Day TWG Workshop Preparation

Friday, 21 February 2020: TWG Breakout Sessions for HIR v2.0
Who should attend: All HIR Technical Working Group members and others interested in participating or learning more about the Heterogeneous Integration Roadmap and participating in interaction, collaboration and feedback.
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30: Registration and refreshments
9:00: HIR Business:     — Vision for v2.0     — Release plan for HIR 2.0
9:30: Four Breakout Sessions A, B, C, D: Inter-TWG Exchange Caucuses
12:00: Lunch (box lunches provided)
1:00 PM – Breakout Sessions E, F, G, H: Inter-TWG Exchange Caucuses
3:30 PM – Closing Remarks and Wrap-Up

We thank our financial supporters for 2020:
   


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