SEMICON/West sessions: The Package is the System … and Enabling Advanced Applications ๐Ÿ—“

โ€” complimentary admission, Expo, CPMT-organized sessions, keynotes, panels …

Morning Session Speakers: Nan Wang, Director of Technology, Cisco; Mike Seddon, MTS, ON Semiconductor; Tim Lee, Technical Fellow, Boeing; Dan Green, PhD, DARPA.
Afternoon Session Speakers: Babak Sabi, PhD, Corporate VP, Intel; CP Hung, PhD, Corporate VP, ASE Group; David McCann, VP, GLOBALFOUNDRIES
Dates: Tuesday, July 11 thru Thursday, July 13 2017; CPMT Sessions on Wednesday, July 12th.
Times Wednesday: 10:30 AM: “The Package is the System is the Product” (5 talks); 2:00 PM: “Advanced Packaging Technologies Enabling Advanced Applications” (4 talks + panel)
EXPO Hours: Tues 10 AM – 5 PM; Wed 10 AM – 5 PM; Thurs 10 AM – 4 PM
Cost: EXPO Pass available at no cost through July 8th (includes the CPMT sessions); other options available.
Location: Moscone Center, S.F.
Reservations: by July 8th
Summary: Log in and register for the EXPO Pass; select the keynotes, talks, sessions, panels, etc, that you’d like to attend. Here are some of the talks:
— MEMS and Sensors: New Intelligence and New Modalities to Drive Next Growth
— World of IoT: Devices & Data
— Material Supply Challenges for Current & Future Leading-edge Devices
— Big Data In Autonomous Driving
— The Package is the System is the Product
— 5G: Advanced Semiconductors and Packaging Technologies
— Advanced Packaging Opportunities and Challenges
— Vision, Alignment, and Execution of Foundry/OSAT Partnerships to Meet Customer Requirements
— … plus many more

System-Level ESD: A New Focus ๐Ÿ—“ ๐Ÿ—บ

— qualification, high-pin-count packages, ESD target levels, co-design, protection challenges, system-efficient ESD design …

Co-sponsored by EDS and CPMT
Speaker: Dr. Charvaka Duvvury, ESD Consulting (and IEEE Distinguished Lecturer)
Meeting Date: Tuesday, July 11, 2017
Time: 6:00 PM Networking with food and refreshments; 6:15 PM Presentation
Cost: none

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: With the continued scaling of technologies, ESD (electrostatic discharge) qualification has become a major challenge. This is mainly due to the demand for higher-speed circuits, mostly implemented in large high pin-count packages, and increased SoC applications. It has already been established that these are having consequences for ESD qualification, requiring a new thrust to change the component ESD target levels. At the same time system level ESD has become much more important, and combining with the new lower ESD target levels system protection is demanding a more thorough understanding with a co-design approach. This is especially the case for USB and HDMI interfaces along with RF applications.
This seminar will give a brief roadmap for component-level ESD levels followed by an overview of the system-level ESD protection challenges. The concept of “system-efficient-ESD-design” (SEED) will be presented to describe a more desirable approach to achieve robust systems while preserving signal integrity. Examples of designing with simulation approaches for both hard and soft ESD failures will be introduced.

Dr. Charvaka Duvvury
Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group. Charvaka is also a Life Fellow of the IEEE. He is currently working as a technical consultant on ESD design methods and ESD qualification support. Charvaka received his PhD in engineering science from the University of Toledo. He has published over 150 papers in technical journals and conferences and holds more than 75 patents. He is a recipient of the IEEE EDS Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), Outstanding Industry Liaison Award twice from the Semiconductor Research Council (1994 and 2012), and IRPS Outstanding Paper Award as well as several Best Paper Awards from the ESD Symposium. He has been a Director on the Board of the ESD Association since 1997. Charvaka also served in the Technical Program Committees of both IEDM and IRPS. He was a contributing editor for the IEEE Transactions on Device and Materials Reliability (TDMR) from 2001-2011. He is a co-founder and has been co-chair of the Industry Council on ESD Target Levels since 2006.

Ten Years of Robustness Validation Applied to Power Electronics Components ๐Ÿ—“ ๐Ÿ—บ

— European car makers, physics of failure, “test to fail”, end-of-life testing, thick wire bonds, planar interconnects …

Speaker: Dr Eckhard Wolfgang, European Center for Power Electronics e.V. (retired from Siemens Research)
Presentation Slides: “Ten Years of Robustness Validation Applied to Power Electronics Components” (4.3 MB PDF)
Meeting Date: Thursday, April 27, 2017
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: The Robustness Validation process is based on the knowledge of the condition of use (mission profile), the physics of failure, and of acceleration models for lifetime prediction. It provides a “test to fail” qualification instead of “test-to pass”, which results in “Fit for Application”. A Team consisted of German auto carmakers, with 1st and 2nd tiers (power module and DC-link) manufacturers, developed qualification specifications, moderated by ZVEI and ECPE. End-of-life tests play an important role together with lifetime models. Advanced technologies consisting of new materials, such as thick copper wire bonds, or planar interconnect schemes, such as silver-sintered or embedded-sandwich modules, however, will show new failure modes and mechanisms which have to be considered for qualification.

Bio: Dr. Eckhard Wolfgang received his PhD in technical physics from the Technical University Vienna in 1970. In the same year he joined Siemens Research at Munich where he stayed until 2016. From 1989 until 2016 he headed the power electronics department. Since then he is working as a consultant for ECPE e.V. (European Center for Power Electronics), mainly in the field of education (Tutorials, Workshops, Conferences like CIPS).

Advances in Low Cost/High Reliability Lead-Free Solder Materials ๐Ÿ—“ ๐Ÿ—บ

— solder’s role, compositions, properties, Ag content, optimum cost/reliability, failure modes …

Speaker: Dr. Ning-Cheng Lee, Vice President of Technology, Indium Corporation
Meeting Date: Thursday, February 23, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation Slides: “Low Cost High Reliability Solder Materials” (1.5 MB PDF)
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: While the electronics industry is advancing rapidly toward miniaturization, two more important drivers actually dictate whether the manufacturers could stay in the game or not — Low Cost, and High Reliability. The former is the ticket to get into the game, while the latter is the ticket to stay in the game. These two drivers exemplified their vital role most astonishingly in solder materials. This talk covers the roles of solder composition on cost, and on reliability. After reviewing the role of Ag in both cost and reliability, the solder materials are reviewed from the lowest cost, zero-Ag solders to composition with higher and higher Ag content. Among all of the alloy options present on the market, including the most recent developments, the representative alloys are introduced with more details, including materials properties, soldering performance, some of the known failure modes, and the primary merit of these alloys.

Bio: Dr. Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has
more than 30 years of experience in the development of fluxes, solder alloys, and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

Intel Silicon Photonics: From Research to Product ๐Ÿ—“ ๐Ÿ—บ

— optical, SiPh, standard silicon processing, performance, low-cost, optical100G transceiver …

Speaker: Dr. Ling Liao, Principal Engineer, Intel
Meeting Date: Wednesday, March 8, 2017
Presentation Slides: “Intel Silicon Photonics: From Research to Product” (1.4 MB PDF)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: Silicon photonics is a breakthrough communications technology that brings optical solutions to the computing industry and can revolutionize the data center. It combines the performance benefits of optical communication and manufacturing capability of silicon CMOS to enable high speed, long reach, small form-factor, and low power connectivity. This talk discusses Intel’s work in researching and developing silicon photonics and the announcement of two Intelยฎ Silicon Photonics 100G optical transceivers for data communications applications.

Bio: Dr. Ling Liao is a Principal Engineer in Intel’s Silicon Photonics Product Division. She joined Intel in 1997 and is a pioneer in silicon high-speed modulation and silicon photonic integration. Her work helped establish Intel as a premier leader in Silicon Photonics (SiPh) technology, and it played a big part in transforming SiPh from being a niche technical interest 15 years ago to the now key enabling technology to revolutionize data communication and data centers.

Copper Pillar, ELK, and Solder: The Challenges of Assembly and Long-Term Reliability at 28nm and 16nm ๐Ÿ—“

— IC packaging, higher metal layers, lower RC constants, current status, assembly issues, potential risks, long-term reliability …

Speaker: Dr. Craig Hillman, CEO, DfR Solutions
Sponsors: SCV Reliability Chapter, with CPMT Chapter
Meeting Date: Thursday, February 9, 2017
Time: Check-in and food at 6:00 PM; Presentation at 6:30 PM
Cost: none (Food sponsored by ICE Labs, ISO 9001 & 17025 Reliability Test Lab)

Location: Qualcomm, Inc., 3165 Kifer Road, Santa Clara
Summary: As always, manufacturing and performance take the forefront in regards to semiconductor packaging. The introduction of copper pillars has helped increase the number of I/Os and current density. The increasing use of ELK and ULK, especially at higher metal layers, has allowed for lower RC constants and better performance. However, both of these changes can come at a cost. A number of companies are reporting challenges with these new structures, especially at 28nm and 16nm process nodes. This presentation will review the current status of copper pillar and ELK, the potential risks both introduce into assembly and long-term reliability, and avenues to evaluate and mitigate any life-limiting mechanisms.

Bio: Dr. Craig Hillman is the Chief Executive Officer of DfR Solutions. DfR Solutions provides engineering services and tools that allow the electronic supply chain to meet customer expectations in regards to quality, reliability, and durability. Over the past 12 years, Dr. Hillman has put together an unrivaled group of subject matter experts in a number of different fields, including semiconductors, batteries, electronic design and assembly, and systems engineering, and has overseen the release of the first Automated Design Analysis software to the EDA/CAE marketplace. DfR Solutions is now the largest organization of its kind in the world and has offices across North America and Europe. Dr. Hillman’s specific expertise is in the development and incorporation of best-in-class product development processes that optimize existing resources and result in strong customer satisfaction. Dr. Hillman holds two patents, has over 100 publications, has won a number of SBIR contracts, has been a guest columnist for Global SMT & Packaging, has been a course instructor at almost all the major electronic conferences (DesignCon, SemiCon, Embedded, IPC, etc.), was identified by the US DoD as a subject matter expert in Pb-free technology, has been an expert witness on over 20 court cases and has worked on a wide variety of quality and reliability issues with over 1000 companies and organizations.

Developing Technology for Autonomous Vehicles and Electric Cars: The Next Platform ๐Ÿ—“ ๐Ÿ—บ

โ€” half-day Workshop: automotive environment, materials, packaging, devices for 5G, LiDAR, RADAR …

(Links to Slides, Below)
Speakers: Professors and Researchers at Georgia Tech/NSF Packaging Research Center (see below)
Sponsored by: CPMT Chapter, with Vehicular Technology Chapter, Technology and Engineering Management Chapter, Photonics Chapter
Workshop Date: Friday, March 24, 2017
Time: 12:30 PM Registration and Networking; 1:00 – 5:30 PM Workshop; 5:45 Reception
Cost: $35 IEEE members. students, unemployed, $50 non-members ($15 more at door)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
For information about exhibiting your technology at this Workshop, please contact Paul Wesling at 408-320-1105.
Summary: This new era of automotive electronics — such as autonomous driving, in-car smartphone-like infotainment, privacy and security, high-speed and high-bandwidth computing, and all-electric cars — requires an entirely differnt vision than is pursued today. There are unprecedented challenges and opportunities to adress these needs with a systematic approach to system scaling, innovative device and package architectures, and heterogeneous integration for the new era, with particular focus on electrical, mechanical, and thermal designs, and new digital, RF, millimeter wave, LiDAR, camera, high-power and high-temperature electronics technologies.
The challenges in this new era are many, and include not only new technologies, but also an educated workforce, supply chain manufacturing, roadmaps, and standards. This workshop will describe the needs and challenges, as well as review the state-of-the-art in R&D and in manufacturing.

Program and Schedule:

Time Details
12:30 Registration/Sign-In and Networking
1:00 The New Era of Automotive Electronics: The Ultimate Electronics System
Presentation Slides: “The New Era of Automotive Electronics: Intro to GaTech PRC Industry Consortium” (5.2 MB PDF)
Prof. Rao Tummala, Director, NSF Packaging Research Center
infotainment, autonomy, innovative architectures, system scaling, design challenges, roadmaps, manufacturing … [more]
Session 1 Computing and Communications Electronics
1:45 2.5D Glass Interposer For Ultra-high Bandwidth Computing
Presentation Slides: “Glass Packaging R&D” (3.2 MB PDF)
Dr Venky Sundaram and Prof Rao Tummala, Georgia Tech
— 2.5D and 3D integration, large panel processing, low cost interposers, through-glass vias, reliability, compliant interconnections, data centers … [more]
2:15 Low- and Medium-Power Electronics
Presentation Slides: “Power Packaging for Computer Applications” (2 MB PDF)
Dr. Raj Pulugurtha and Prof Rao Tummala, Georgia Tech
— IVR, DC-DC converters, substrate-embedded inductors, transformers and capacitors, high-temp and high-voltage capacitors … [more]
2:45 Coffee, Tea Break; Networking and Exhibitor Interactions
3:15 5G Communications with Glass Embedding and Fanout
Presentation Slides: “5G (28-40 GHz) Substrates and Antennas” (.5 MB PDF) and “5G Communications with Glass Embedding and Fanout” (6 MB PDF)
Prof. Emmanouil Tentzeris, Dr. Venky Sunraram and Dr. Raj Pulugurtha, Georgia Tech
— Advanced 5G substrates, package-integrated antennas, low-loss and precision 5G transmission lines, passive components … [more]
Session 2 Sensing Electronics
3:45 Devices and 3D Glass Fanout Package for Next Generation Radar, Lidar and Camera
Presentation Slides: “Autonomous Cars: Radar, Lidar, Stereo Cameras” (4 MB PDF)
Dr. Venky Sundaram, Dr. Chris Valenta, Prof. Peter Hesketh and Prof. John Cressler, Georgia Tech
— sensor fusion, SiGe devices, low-cost LiDAR packaging, hermetic and near-hermetic glass packages for sensors, design for reliability … [more]
Session 3 Devices, Packaging and High-Temperature Materials for Power Electronics in Electric Cars
4:15 High-Power and High-Temperature Electronics for Electric Cars
Presentation Slides: “High-Power Devices, High-Temperature Materials and Packaging for Electric Cars” (5 MB PDF)
Prof. Shyh-Chiang Shen, Dr. Vanessa Smet and Dr. Raj Pulugurtha, Georgia Tech
— Packaging for 150-250 C, high-temp dielectrics and mold compounds, high-temp substrates and fan-out packages … [more]
Moderator: Paul Wesling
— Questions, observations, future directions
Refreshments and Networking
— snacks and drinks
— Meet our exhibitors
— Consult with the speakers
6:30 Dismissal

Wafer-Level Process Formation of a Polymer-Isolated Chip-Scale Package ๐Ÿ—“ ๐Ÿ—บ

โ€” yield loss, leakage, sidewall insulation, protection, reliability results …

Speaker: Harry Gee, ON Semiconductor
Presentation Slides: “Wafer-Level Process Formation of a Polymer-Isolated Chip-Scale Package” (1 MB PDF)
Meeting Date: Tuesday, November 22, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: Small-footprint (0201/01005 size) bare silicon chip-scale package (CSP) after board assembly has yield loss due to high leakage between an I/O pad and the silicon substrate. The solder paste applied at assembly can inadvertently extend out and touch the exposed silicon along the sidewall of the CSP device. After reflow, this excess solder may cause a high leakage path or short between an I/O pad and the silicon of the CSP device. Small-footprint CSP devices normally have I/O pads that are short and close to the CSP die edge. The short bump height and the proximity to the die edge increase the chance for a solder short to the silicon substrate along the sidewall. In this talk, we present a wafer-level backend process flow to make a 0201/01005 CSP device such that the silicon sidewalls and backside are completely covered by a thin non-conducting polymer material. The polymer-isolated CSP solution provides complete electrical insulation to the active silicon. This eliminates solder-to-silicon sidewall leakage yield loss after board assembly. The polymer offers protection to the active silicon device from assembly handling to prevent die cracking and chip-out. We will present assembly electrical yield and board level reliability results for this polymer-isolated CSP device made by wafer level processing.
Bio: Harry Gee is presently a Device Engineer at ON Semiconductor. He received his B.S. degree in Chemical Engineering from the University of California, Berkeley. He has been active in the semiconductor industry for over thirty years as Process, Device, and Development engineer. He has worked with Wafer-Level Chip-Scale Packaging (WLCSP) for the past sixteen years on numerous products from discrete parts to large analog/logic chips.

Advances in Plasma Nano-coating ๐Ÿ—“ ๐Ÿ—บ

โ€” properties, density, pinhole-free, thicknesses, corrosion resistant, environmentally benign …

Speaker: Abe Ghanbari PhD, Chief Solutions Officer, Semblant
Presentation Slides: “Advances in Plasma Nano-coating” (3 MB PDF)
Meeting Date: Tuesday, November 8, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: Plasma nano-coatings, due to their inherently superior properties, are rapidly finding new applications in a multitude of industries. This includes consumer electronics, automotive, industrial, semiconductor and medical.
In plasma coating, a nano-scale organic or inorganic layer is formed over the entire surface area of an object placed in the plasma. The coating process is relatively simple and does not require any curing once the coating is completed. In general, the coatings tend to be highly dense and pinhole-free. Most of the coatings produced are colorless and odorless and can be easily formed with thicknesses ranging from 100s of ร… to several ยต. The coatings adhere to variety of substrate materials on an atomic scale and do not affect the look and feel of the substrates.
By developing the right combination of plasma coating technology and polymers, we have been able to achieve multi-layer liquid repellent, galvanic corrosion resistance and environmentally benign coatings. In this presentation, we will describe the technology and process of our PlasmaShieldยฎ with high volume mass production traction characteristics in enhancing the reliability of the devices used in consumer electronics.

Bio: Dr. Abe Ghanbari is Chief Solutions Officer at Semblant since 2012. Prior to Semblant, Abe was VP at NovaSolar Technologies, where he led development and deployment of solar processing technologies and equipment for Chinaโ€™s factory. Abe started his career in R&D at Varian Corporation, followed by a variety of product development and general management roles at Sony, Applied Materials and VLOC Corp. He currently serves on the advisory board of several technology centers, start-ups and well-established companies. Throughout his career, he has developed technologies, products and processes that provide solutions to meet the needs of customers in emerging markets.
Abe holds a Ph.D. in engineering & applied physics, Cornell University, M.S. in plasma science, and B.S. in electrical engineering from the University of Illinois, M.B.A. from Saint Maryโ€™s College with emphasis in operations and marketing, management. He is a holder of eight patents.

Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging ๐Ÿ—“ ๐Ÿ—บ

โ€” wafer level, molding, encapsulant, warpage control, lower cost …

Speaker: Eric Kuah, VP of Technology, ASM
Meeting Date: Wednesday, October 19, 2016
Presentation Slides: “Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging” (5 MB PDF)
Time: 5:45 PM Registration (and sandwiches/drinks); 6:30 PM Presentation
Presentation-only: 6:30 PM (come at 6:15)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara

Summary: The discrete package production is a very sizeable market, offering many different packages for a variety of applications such as ESD protection, MOSFETS among others. These packages act as a function for voltage/current protection, electrical/electronic filtering, and power efficiency improvement. The current packaging and assembly methodologies use leadframe to produce packages such as DSN, DFN, SOD and SOT. The advent of producing these packages on either the wafer or panel level format has arrived. In our recent packaging and assembly work we found that producing discrete package using wafer level format is feasible from the perspective of cost of production and technology . From the viewpoint of cost production, a significant portion of the manufacturing process can be eliminated, for instance interconnected technologies using wire bonding. This will translate into a reduction in cost of production and an increased throughput. In the aspect of technology, power efficiency can be further improved. Take for an example, a DSN. A real estate of 30mm2 with a power density of 60 mW/mm2 can be reduced to a smaller real estate of 1.1mm2 with a power density of 1000 mW/mm2. The focus of our presentation is to share our experience in producing such package, and in particular encapsulation. We will discuss the challenges and solutions that a packaging/equipment engineer will face during the molding process of these discrete packages at a wafer level. Technical solutions to be discussed are material handling, encapsulation tool design, encapsulant selection, warpage control, voiding, and moldability solutions. The package format of our work is carried out on an 8โ€ silicon wafer that allows one to produce it as either a 5S (five-sided package) or 6S (six-sided package) discrete package.

Bio: Eric Kuah has been the Vice President of Technology at the Encapsulation Solutions Group of ASM since 1993. He received his BSME (summa cum laude) and MSME from Ohio University (Athens) in 1985 and 1987, respectively, and a second Masters in Theoretical and Applied Mechanics from the University of Illinois (Urbana-Champaign) in 1993. In 2000, Eric earned his MBA in Management of Technology from Nanyang Technological University, and was awarded the Singapore Institute of Engineer Gold medal.