Heterogeneous Packaging Integration for Electronics Systems ๐Ÿ—“ ๐Ÿ—บ

— mobile products, system-on-chip, dissimilar chips, performance, cost, SiP, TSV, interposers, forecast …

Speaker: Dr. John H Lau, ASM Pacific Technology
Presentation Slides: “Fan-Out Wafer-Level Packaging
for 3D IC Heterogeneous Integration”
(3.4 MB PDF)
Meeting Date: Thursday, January 25, 2018
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only (no cost): 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1801eps.eventbrite.com

Summary: Because of the drive of Moore’s law, compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. It has been a very “fancy” name in semiconductor packaging for the past few years. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem, rather than integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more implementations of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and lower gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

SoC: Apple’s application processor (A10 and A11)
SiP: Amkor’s SiP for automobiles; Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with SoW (System-on-Wafer): Leti’s SoW; ULCA’s SoW
Heterogeneous Integration with TSV-Interposers: TSMC/Xilinx’s CoWoS; AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer; Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer: Xilinx/SPIL’s TSV-less SLIT; SPIL/Xilinx’s TSV-less NTI; Amkor’s TSV-less SLIM; ASE’s TSV-less FOCoS; MediaTek’s TSV-less RDLs by FOWLP; Intel’s TSV-less EMIB; Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM; Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer; Cisco/eSilicon’s TSV-less Organic Interposer; ITRI’s TSV-less TSH; Shinko’s TSV-less i-THOP

Bio: John H. Lau has been a senior technical advisor of ASM since 2014, an ITRI Fellow of Industrial Technology Research Institute for 4.5 years, a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME Singapore for 2 years and a Senior Scientist/MTS at HPLab/Agilent in California for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on flip chip technologies, WLCSP, BGA, TSV for 3D integration, advanced MEMS packaging, and reliability of 2D and 3D IC interconnections. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Mold Compound Interactions in Cu-Al Wirebonded ICs Operating in Harsh Environments ๐Ÿ—“ ๐Ÿ—บ

— high reliability, intermetallic growth, bond interface, formulations, temperature, bias, predictive model …

Speaker: Luu Nguyen, TI Fellow, Texas Instruments
Meeting Date: Thursday, October 26, 2017 (changed from Sept. 13th)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1710cpmt.eventbrite.com
Summary: For high-reliability applications in harsh environments, better understanding of the acceleration factors under the stresses of operation is required. Prolonged exposure of copper wires at elevated temperatures can result in excessive intermetallic growth and degradation of the bond interface. Mold compounds used for encapsulation can vary widely in their formulations including ionic content, pH, porosity, and diffusion rates. Selection of the right material combination plays a key role in defining the lifetime of the wirebonded system. This talk will discuss the combined effect of various operational parameters such as temperature and bias, along with material properties, in the development of a model to predict the remaining useful life of Cu-wirebonded packages.

Bio: Dr. Luu Nguyen is a TI Fellow at Texas Instruments, working on printed electronics, wafer level packaging, high-voltage packaging, and design for manufacturability. He received his Ph.D. in Mechanical Engineering from MIT, and has worked at IBM Research and Philips Research. He coedited two books on packaging, and has over 200 publications. He has over 70 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He received two Best of Conference Awards, one Best Poster of Conference Award, and eight IMAPS and IEMT Best of Session Conference Awards. He received the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award. Other awards also include the 2003, 2014, 2015, and 2016 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer.

Comparison of Die Singulation Techniques ๐Ÿ—“ ๐Ÿ—บ

— die thinning, stealth laser, laser abrasion, plasma etch, rotary blade, results …

Speaker: Dr. Annette Teng, Chief Technology Officer, Promex Industries
Presentation Slides: “Comparison of Singulation Techniques” (5 MB PDF)
Meeting Date: Thursday, September 28, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1709bcpmt.eventbrite.com
Summary: Wafer thinning and singulation is a critical process for successful miniaturization and high density packaging. A comparison of the latest die singulation techniques will be presented based on dicing yields and cost. These include stealth laser, laser abrasion, plasma etch and conventional rotary blade. Some results of stealth laser on singulated II-VI and III-V type dies will be presented in collaboration with Disco.

Bio: Annette Teng is currently the Chief Technology Officer at Promex Industries, which is a fast-turn subcontractor located in Silicon Valley. She has previously worked in components packaging and assembly at Philips Semiconductor, Linear Technology and Corwil Technology. Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years. She also worked at the Hong Kong University of Science and Technology to initiate their electronics packaging programs in 1997 to 2000. She has been active in IEEE-EPS (CPMT) activities locally and overseas. She is currently the Chair of the IEEE-EPS (CPMT) Santa Clara Valley/Bay Area Chapter.
She graduated with a Ph.D. in Materials Engineering from University of Virginia after receiving a BS from Sweet Briar College.

How to Peel Ultra-Thin Dies from Wafer Tape ๐Ÿ—“ ๐Ÿ—บ

— bending stress, die strength, peel force, die structures, wafer processing steps, TSVs, pickup methods, experimental verification …

Speaker: Dr. Stefan Behler, Senior Expert Process Engineer, Besi Switzerland AG
Presentation Slides: “How To Peel Ultra Thin Dies From Wafer Tape” (1 MB PDF)
Meeting Date: Thursday, December 7, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1712cpmt.eventbrite.com
Summary: The four major key properties for successful, damage-free ultra-thin die (< 50 um thick) pickup from a wafer foil are described in detail: die bending stress, die strength, edge peel force, and bulk peel force. First, bending stress for different pickup methods (multi stage, multi disc, multi needle) are calculated and compared using a dynamic FEA model. Second, we summarize how the die strength is influenced by die structures and wafer processing steps, especially by thinning and dicing methods. In addition, we present die strength measurements for TSV test dies. Third, the property "wafer foil edge peel force" is introduced, and the dependency on the dicing method is experimentally verified. It clearly shows, that dicing-before-grinding is to be preferred over single cut dicing. Fourth, we give an overview of bulk peel forces of various commercial wafer foils. Values are taken from datasheet specifications, and compared using Kendallโ€™s equation. Bio: Stefan Behler received his M. S. in experimental physics from the University of Gรถttingen (Gemany) in 1990, and his Ph.D. in physics from the University of Basel (Switzerland) in 1994. He was awarded an Alexander von Humboldt fellowship for a 2-year research project at the Lawrence Berkeley National Laboratory. The project was aimed at the investigation of surface chemistry of noble metals. In 1996 he joined the company Besi (formerly ESEC) focusing on process technology of die bonding. He is currently project manager for ultra-thin die applications at Besi Switzerland.

Recent Progress in Memory Technology Reliability ๐Ÿ—“ ๐Ÿ—บ

— higher performance, densities, novel materials, cell to packaging level, failure modes, underlying physics …

Speaker: Dr. Bob Gleixner, Micron Technology Inc.
Presentation Slides: “title” (xx MB PDF) after meeting
Meeting Date: Tuesday, August 8, 2017
Time: 6:00 PM food/refreshments and networking; 6:15 PM Presentation
Cost: none

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-eds
Summary: As they continue to pursue higher performance and densities at lower cost, semiconductor memory technologies have introduced novel materials and integration schemes from the cell to the packaging level. Understanding the reliability failure modes associated with these materials and processes is critical to providing a robust memory component. This presentation will review the major technology directions taking place in the areas of DRAM, NAND, and emerging memories. It will then review recent publications that identify the reliability concerns posed by these directions, with an emphasis on those that attempt to discern the underlying physics.

Bio: Bob Gleixner received his Ph.D. degree in materials science from Stanford University in 1998. He then joined Intel and for the next ten years worked on reliability characterization of microprocessor, microdisplay, and non-volatile memory technologies and products. Starting in 2004 Bobโ€™s work focused on developing and productizing advanced Phase Change Memory technologies, first at Intel and later with Numonyx. He joined Micron in 2010 as part of the Numonyx acquisition, where he is now a Distinguished Member of the Technology Staff. While at Micron heโ€™s managed teams of silicon technology and product development engineers, with his main focus on the reliability of novel non-volatile memory technologies. He has published 13 technical papers and received 5 US patents.

SEMICON/West sessions: The Package is the System … and Enabling Advanced Applications ๐Ÿ—“

โ€” complimentary admission, Expo, CPMT-organized sessions, keynotes, panels …

Morning Session Speakers: Nan Wang, Director of Technology, Cisco; Mike Seddon, MTS, ON Semiconductor; Tim Lee, Technical Fellow, Boeing; Dan Green, PhD, DARPA.
Afternoon Session Speakers: Babak Sabi, PhD, Corporate VP, Intel; CP Hung, PhD, Corporate VP, ASE Group; David McCann, VP, GLOBALFOUNDRIES
Dates: Tuesday, July 11 thru Thursday, July 13 2017; CPMT Sessions on Wednesday, July 12th.
Times Wednesday: 10:30 AM: “The Package is the System is the Product” (5 talks); 2:00 PM: “Advanced Packaging Technologies Enabling Advanced Applications” (4 talks + panel)
EXPO Hours: Tues 10 AM – 5 PM; Wed 10 AM – 5 PM; Thurs 10 AM – 4 PM
Cost: EXPO Pass available at no cost through July 8th (includes the CPMT sessions); other options available.
Location: Moscone Center, S.F.
Reservations: www.xpressreg.net/register/semi0717/start.asp?sc=IEEE17EXT by July 8th
Summary: Log in and register for the EXPO Pass; select the keynotes, talks, sessions, panels, etc, that you’d like to attend. Here are some of the talks:
— MEMS and Sensors: New Intelligence and New Modalities to Drive Next Growth
— World of IoT: Devices & Data
— Material Supply Challenges for Current & Future Leading-edge Devices
— Big Data In Autonomous Driving
— The Package is the System is the Product
— 5G: Advanced Semiconductors and Packaging Technologies
— Advanced Packaging Opportunities and Challenges
— Vision, Alignment, and Execution of Foundry/OSAT Partnerships to Meet Customer Requirements
— … plus many more

System-Level ESD: A New Focus ๐Ÿ—“ ๐Ÿ—บ

— qualification, high-pin-count packages, ESD target levels, co-design, protection challenges, system-efficient ESD design …

Co-sponsored by EDS and CPMT
Speaker: Dr. Charvaka Duvvury, ESD Consulting (and IEEE Distinguished Lecturer)
Meeting Date: Tuesday, July 11, 2017
Time: 6:00 PM Networking with food and refreshments; 6:15 PM Presentation
Cost: none

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: sites.ieee.org/scv-eds
Summary: With the continued scaling of technologies, ESD (electrostatic discharge) qualification has become a major challenge. This is mainly due to the demand for higher-speed circuits, mostly implemented in large high pin-count packages, and increased SoC applications. It has already been established that these are having consequences for ESD qualification, requiring a new thrust to change the component ESD target levels. At the same time system level ESD has become much more important, and combining with the new lower ESD target levels system protection is demanding a more thorough understanding with a co-design approach. This is especially the case for USB and HDMI interfaces along with RF applications.
This seminar will give a brief roadmap for component-level ESD levels followed by an overview of the system-level ESD protection challenges. The concept of “system-efficient-ESD-design” (SEED) will be presented to describe a more desirable approach to achieve robust systems while preserving signal integrity. Examples of designing with simulation approaches for both hard and soft ESD failures will be introduced.

Dr. Charvaka Duvvury
Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group. Charvaka is also a Life Fellow of the IEEE. He is currently working as a technical consultant on ESD design methods and ESD qualification support. Charvaka received his PhD in engineering science from the University of Toledo. He has published over 150 papers in technical journals and conferences and holds more than 75 patents. He is a recipient of the IEEE EDS Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), Outstanding Industry Liaison Award twice from the Semiconductor Research Council (1994 and 2012), and IRPS Outstanding Paper Award as well as several Best Paper Awards from the ESD Symposium. He has been a Director on the Board of the ESD Association since 1997. Charvaka also served in the Technical Program Committees of both IEDM and IRPS. He was a contributing editor for the IEEE Transactions on Device and Materials Reliability (TDMR) from 2001-2011. He is a co-founder and has been co-chair of the Industry Council on ESD Target Levels since 2006.

Ten Years of Robustness Validation Applied to Power Electronics Components ๐Ÿ—“ ๐Ÿ—บ

— European car makers, physics of failure, “test to fail”, end-of-life testing, thick wire bonds, planar interconnects …

Speaker: Dr Eckhard Wolfgang, European Center for Power Electronics e.V. (retired from Siemens Research)
Presentation Slides: “Ten Years of Robustness Validation Applied to Power Electronics Components” (4.3 MB PDF)
Meeting Date: Thursday, April 27, 2017
Time: 11:30 AM Registration (and pizza/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1704cpmt.eventbrite.com
Summary: The Robustness Validation process is based on the knowledge of the condition of use (mission profile), the physics of failure, and of acceleration models for lifetime prediction. It provides a “test to fail” qualification instead of “test-to pass”, which results in “Fit for Application”. A Team consisted of German auto carmakers, with 1st and 2nd tiers (power module and DC-link) manufacturers, developed qualification specifications, moderated by ZVEI and ECPE. End-of-life tests play an important role together with lifetime models. Advanced technologies consisting of new materials, such as thick copper wire bonds, or planar interconnect schemes, such as silver-sintered or embedded-sandwich modules, however, will show new failure modes and mechanisms which have to be considered for qualification.

Bio: Dr. Eckhard Wolfgang received his PhD in technical physics from the Technical University Vienna in 1970. In the same year he joined Siemens Research at Munich where he stayed until 2016. From 1989 until 2016 he headed the power electronics department. Since then he is working as a consultant for ECPE e.V. (European Center for Power Electronics), mainly in the field of education (Tutorials, Workshops, Conferences like CIPS).

Advances in Low Cost/High Reliability Lead-Free Solder Materials ๐Ÿ—“ ๐Ÿ—บ

— solder’s role, compositions, properties, Ag content, optimum cost/reliability, failure modes …

Speaker: Dr. Ning-Cheng Lee, Vice President of Technology, Indium Corporation
Meeting Date: Thursday, February 23, 2017
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation Slides: “Low Cost High Reliability Solder Materials” (1.5 MB PDF)
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1702cpmt.eventbrite.com
Summary: While the electronics industry is advancing rapidly toward miniaturization, two more important drivers actually dictate whether the manufacturers could stay in the game or not — Low Cost, and High Reliability. The former is the ticket to get into the game, while the latter is the ticket to stay in the game. These two drivers exemplified their vital role most astonishingly in solder materials. This talk covers the roles of solder composition on cost, and on reliability. After reviewing the role of Ag in both cost and reliability, the solder materials are reviewed from the lowest cost, zero-Ag solders to composition with higher and higher Ag content. Among all of the alloy options present on the market, including the most recent developments, the representative alloys are introduced with more details, including materials properties, soldering performance, some of the known failure modes, and the primary merit of these alloys.

Bio: Dr. Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has
more than 30 years of experience in the development of fluxes, solder alloys, and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

Intel Silicon Photonics: From Research to Product ๐Ÿ—“ ๐Ÿ—บ

— optical, SiPh, standard silicon processing, performance, low-cost, optical100G transceiver …

Speaker: Dr. Ling Liao, Principal Engineer, Intel
Meeting Date: Wednesday, March 8, 2017
Presentation Slides: “Intel Silicon Photonics: From Research to Product” (1.4 MB PDF)
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1703acpmt.eventbrite.com
Summary: Silicon photonics is a breakthrough communications technology that brings optical solutions to the computing industry and can revolutionize the data center. It combines the performance benefits of optical communication and manufacturing capability of silicon CMOS to enable high speed, long reach, small form-factor, and low power connectivity. This talk discusses Intel’s work in researching and developing silicon photonics and the announcement of two Intelยฎ Silicon Photonics 100G optical transceivers for data communications applications.

Bio: Dr. Ling Liao is a Principal Engineer in Intel’s Silicon Photonics Product Division. She joined Intel in 1997 and is a pioneer in silicon high-speed modulation and silicon photonic integration. Her work helped establish Intel as a premier leader in Silicon Photonics (SiPh) technology, and it played a big part in transforming SiPh from being a niche technical interest 15 years ago to the now key enabling technology to revolutionize data communication and data centers.