Advances in Plasma Nano-coating ๐Ÿ—“ ๐Ÿ—บ

โ€” properties, density, pinhole-free, thicknesses, corrosion resistant, environmentally benign …

Speaker: Abe Ghanbari PhD, Chief Solutions Officer, Semblant
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Presentation Slides: “Advances in Plasma Nano-coating” (3 MB PDF)
Meeting Date: Tuesday, November 8, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1611lcpmt.eventbrite.com
Summary: Plasma nano-coatings, due to their inherently superior properties, are rapidly finding new applications in a multitude of industries. This includes consumer electronics, automotive, industrial, semiconductor and medical.
In plasma coating, a nano-scale organic or inorganic layer is formed over the entire surface area of an object placed in the plasma. The coating process is relatively simple and does not require any curing once the coating is completed. In general, the coatings tend to be highly dense and pinhole-free. Most of the coatings produced are colorless and odorless and can be easily formed with thicknesses ranging from 100s of ร… to several ยต. The coatings adhere to variety of substrate materials on an atomic scale and do not affect the look and feel of the substrates.
By developing the right combination of plasma coating technology and polymers, we have been able to achieve multi-layer liquid repellent, galvanic corrosion resistance and environmentally benign coatings. In this presentation, we will describe the technology and process of our PlasmaShieldยฎ with high volume mass production traction characteristics in enhancing the reliability of the devices used in consumer electronics.


Bio: Dr. Abe Ghanbari is Chief Solutions Officer at Semblant since 2012. Prior to Semblant, Abe was VP at NovaSolar Technologies, where he led development and deployment of solar processing technologies and equipment for Chinaโ€™s factory. Abe started his career in R&D at Varian Corporation, followed by a variety of product development and general management roles at Sony, Applied Materials and VLOC Corp. He currently serves on the advisory board of several technology centers, start-ups and well-established companies. Throughout his career, he has developed technologies, products and processes that provide solutions to meet the needs of customers in emerging markets.
Abe holds a Ph.D. in engineering & applied physics, Cornell University, M.S. in plasma science, and B.S. in electrical engineering from the University of Illinois, M.B.A. from Saint Maryโ€™s College with emphasis in operations and marketing, management. He is a holder of eight patents.

Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging ๐Ÿ—“ ๐Ÿ—บ

โ€” wafer level, molding, encapsulant, warpage control, lower cost …

Speaker: Eric Kuah, VP of Technology, ASM
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Meeting Date: Wednesday, October 19, 2016
Presentation Slides: “Wafer Level Encapsulation – Challenges And Solutions on an Alternative Format for Discrete Packaging” (5 MB PDF)
Time: 5:45 PM Registration (and sandwiches/drinks); 6:30 PM Presentation
Presentation-only: 6:30 PM (come at 6:15)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1610cpmt.eventbrite.com

Summary: The discrete package production is a very sizeable market, offering many different packages for a variety of applications such as ESD protection, MOSFETS among others. These packages act as a function for voltage/current protection, electrical/electronic filtering, and power efficiency improvement. The current packaging and assembly methodologies use leadframe to produce packages such as DSN, DFN, SOD and SOT. The advent of producing these packages on either the wafer or panel level format has arrived. In our recent packaging and assembly work we found that producing discrete package using wafer level format is feasible from the perspective of cost of production and technology . From the viewpoint of cost production, a significant portion of the manufacturing process can be eliminated, for instance interconnected technologies using wire bonding. This will translate into a reduction in cost of production and an increased throughput. In the aspect of technology, power efficiency can be further improved. Take for an example, a DSN. A real estate of 30mm2 with a power density of 60 mW/mm2 can be reduced to a smaller real estate of 1.1mm2 with a power density of 1000 mW/mm2. The focus of our presentation is to share our experience in producing such package, and in particular encapsulation. We will discuss the challenges and solutions that a packaging/equipment engineer will face during the molding process of these discrete packages at a wafer level. Technical solutions to be discussed are material handling, encapsulation tool design, encapsulant selection, warpage control, voiding, and moldability solutions. The package format of our work is carried out on an 8โ€ silicon wafer that allows one to produce it as either a 5S (five-sided package) or 6S (six-sided package) discrete package.


Bio: Eric Kuah has been the Vice President of Technology at the Encapsulation Solutions Group of ASM since 1993. He received his BSME (summa cum laude) and MSME from Ohio University (Athens) in 1985 and 1987, respectively, and a second Masters in Theoretical and Applied Mechanics from the University of Illinois (Urbana-Champaign) in 1993. In 2000, Eric earned his MBA in Management of Technology from Nanyang Technological University, and was awarded the Singapore Institute of Engineer Gold medal.

Roll-to-roll Manufacturing in Electronics: Making it Work ๐Ÿ—“ ๐Ÿ—บ

โ€” charge-array, deposition, registration, evolution, flip-chip and TFTs …

โ€”- NOTE CHANGE OF MEETING ROOM —
Speaker: Peter C Salmon, Salmon Engineering
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Presentation Slides: “Roll-to-roll Manufacturing in Electronics: Making it Work” (1 MB PDF)
Meeting Date: Tuesday, January 10, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members
Location: (Download MAP) Texas Instruments Building C, Big Sur Room, 3689 Kifer Rd, Santa Clara
Reservations: 1701cpmt.eventbrite.com


Summary:

Summary: A new concept for roll-to-roll fabrication is presented. A key component of each deposition station in the proposed roll-to-roll system is a charge-array wafer. The charge-array wafer enables two disruptive innovations: 1) “active registration” wherein the target substrate is continually seeking precise alignment, even as it moves through a deposition station; and 2) electronic programming of the desired pattern for each deposition layer.
A potential product evolution is described, beginning with flexible printed circuits (FPCs) having 1-mil line and space. Then FPCs with embedded passives, Hybrid Electronic Systems (HES) having attached flip chips, and finally complex electronic systems incorporating FPCs, embedded passives, flip chips, and thin-film transistors. The complex systems may include novel structures that are not currently found on PCBs.


Bio: Peter Salmon received his BE degree in Electrical Engineering from Auckland University, New Zealand. He emigrated to the United States and obtained MSEE and EE degrees at Northeastern University. He has enjoyed an eclectic career, including 10 years at Intel and Fairchild Semiconductor as a chip designer, 10 years at TRW and GTE as a systems engineer for large defense systems, almost 10 years founding startup companies involving thermal and electrostatic printing technologies, and a few more years as an engineering consultant and expert witness. He is a co-founder of i-Blades, Inc. which is pioneering new markets in attachments to smart phones; he developed the base technology for magnetic and electrical coupling. He has been awarded a first patent on his roll-to-roll technology, and a second one is pending.

Embedding and Miniaturization in Electronics Packaging ๐Ÿ—“ ๐Ÿ—บ

โ€” market needs, form-factors. wearables, cameras, consumer electronics, power converters …

โ€” market needs, form-factors. wearables, cameras, consumer electronics, power converters …
Speaker: Wolfram Zotter, Sales Engineering, AT&S Americas LLC
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Presentation Slides: “Embedding and Miniaturization in Electronics Packaging” (1.6 MB PDF)
Meeting Date: Tuesday, August 9, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1608l1cpmt.eventbrite.com
Summary: Miniaturization is quite a topic these days but it’s far more than simply shrinking form-factors. Accommodating market needs featuring products like Wearables, Cameras, Consumer electronics, Power converters and many more applications require additional features such as solutions for form-factor, reliability, thermal needs and efficiency improvements. Within this talk we will see how embedding technology (ECP) can cater to those needs as well as why it can solve and help with individual and very specific needs.

Bio: Wolfram Zotter is currently heading the US Engineering group within AT&S Americas LLC. This group takes Field-application-engineering responsibilities and also involves in technology and solution promotion. Wolfram started at AT&S in 2002 responsible for production front-end, where he was able to gather basic know-how and experience. Later he was involved and lead teams within AT&S across multiple locations globally and made sure that market needs would be addressed with proper technologies. Since moving to the US in 2008 he has been heavily engaged with local OEMs as well as CEMs and ODMs.

A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP ๐Ÿ—“ ๐Ÿ—บ

โ€” TC bonding, drivers, accuracy, platform, advanced processes …

โ€” TC bonding, drivers, accuracy, platform, advanced processes …
Speaker: Tom Strothmann, Director, Advanced Packaging Next-Gen Products, Kulicke & Soffa Industries
Presentation Slides: “A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP “ (700 kB PDF)
Meeting Date: Thursday, February 25, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1602l2cpmt.eventbrite.com
Summary: Assembly with thermocompression bonding (TCB) enables the next generation fine pitch 2.5D and 3D products using Cu pillar interconnects, but the industry has been slow to invest in the dedicated infrastructure required for the process. TCB volume today is driven primarily by the memory market and stacked DRAM packages, including the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) products; however, the extreme placement accuracies required for TC bonding can be leveraged to enable improved capability for other assembly processes as well. With only minor modifications, the same equipment used for TCB assembly can also be used for highly accurate die placement in Fan-out Wafer Level Packages (FOWLP) and die placement for mass reflow processes with pitches as low as 30um. The flexibility inherent in new tool designs ensures cost effective HVM capability for TCB as well a manufacturing platform with the ability to adapt to product mix changes over time. The same tool purchased for Flip Chip or FOWLP die placement today can be configured to run HVM TCB 2.5D or 3D later. This presentation will review the performance of this flexible manufacturing platform over a range of Advanced Packaging processes.

Bio: Tom Strothmann is the Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major Asian OSATS. Tom has over 30 years of experience in semiconductor manufacturing, including extensive experience in both wafer fabrication and flip chip wafer level packaging.

Recent Advances and Trends in Semiconductor Packaging ๐Ÿ—“ ๐Ÿ—บ

– fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …

– fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …
Speaker: Dr. John H. Lau, Sr. Technical Advisor, ASM
Slides: Download here (3 MB PDF)
Date: Tuesday, April 12, 2016
Time: 11:300 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1604lcpmt.eventbrite.com
Summary: Recent advances in, for example, fan-out wafer/panel level packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration are examined and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.


Bio: John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at Hewlett-Packard/Agilent for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 20 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration (2013), and 3D IC Integration and Packaging (2015). He is an IEEE Fellow and ASME Fellow.

Package Requirements for High-Speed Systems ๐Ÿ—“ ๐Ÿ—บ

โ€” SiP solution, enabling technologies, applications, packaging, market segments …

โ€” SiP solution, enabling technologies, applications, packaging, market segments …
Presentation Slides: “Package Requirements for High-Speed Systems” (3.7 MB PDF)
Speaker: Dr. Dongkai Shangguan, CMO, STATS ChipPAC
Meeting Date: Thursday, April 28, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1604l2.eventbrite.com
Summary: System-in-package (SiP) technology has been evolving through the utilization of various packaging technology building blocks to serve the market’s needs, with respect to miniaturization, heterogeneous integration, modularization, and smaller form factor, with the added benefits of lower cost and faster time to-market, as compared with SoC solutions. In this presentation, integration of advanced packaging technologies for the optimum SiP solution will be discussed, and enabling technologies for product solutions will be outlined for different applications and market segments.


Bio: Dr. Dongkai Shangguan is currently the Chief Marketing Officer of STATS ChipPAC, after having served as the Founding CEO of the National Center for Advanced Packaging Co., Ltd. (“NCAP China”). Previously, Dongkai worked for 10 years at the Electronics Operations with Ford Motor Co. in various technical and management functions, and for 11 years at Flextronics as Corporate Vice President of Global Advanced Technology and Engineering Leadership.
Dr. Shangguan, an IEEE Fellow, has served on the IEEE CPMT Society Board of Governors, the IPC Board of Directors, the Advisory Board of the Sustainable Electronics Manufacturing (SEM) Working Group, etc. Dongkai has received a number of recognitions for his contributions to the industry, including the “Outstanding Sustained Technical Contribution Award” from IEEE CPMT, “Leadership Award” from the Sustainable Electronics Manufacturing Working Group, “Presidentรขโ‚ฌโ„ขs Award” from IPC, “Total Excellence in Electronics Manufacturing Award” from the Society of Manufacturing Engineers (SME), and the “Soldertec Lead-Free Soldering Award”.
Dongkai received his BS degree in Mechanical Engineering from Tsinghua University, China; Ph.D. degree in Materials from the University of Oxford, U.K.; and MBA degree from the San Jose State University. He conducted post-doctoral teaching and research at the University of Cambridge and The University of Alabama, and is currently a Guest Professor at several universities. Dr. Shangguan has published two books and authored/co-authored 250 technical papers and articles, and has over 20 patents issued.