Device-Circuit Interaction in Advanced Technology Nodes 🗓 🗺

— EDS Symposium – deep learning, 5nm node, co-optimization, power circuits, package integration …

Meeting Date: Friday, November 11, 2016
Time: 1:00 PM to 5:30 PM
Cost: $22 for students, $43 for IEEE members, $64 for non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Summary: This symposium will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes, and consists of talks from five distinguished speakers:
1. Hardware for Deep Learning, Dr. William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor
2. Design-Technology Co-Optimization for 5nm Node and Beyond, Dr. Victor Moroz, Scientist, Synopsys
3. Chip Design and Process Co-optimizations, Design for Manufacturing/Reliability in Advanced Technology Nodes, Dr. John Hu, Director, Advanced Technology, Nvidia Corporation
4. Process Requirements for Integrated Power Circuits, Dr. Kevin Scoones, Fellow, Texas Instruments
5. 2.5D/3D Package Integration: Technology Trends, Challenges and Applications, Dr. Suresh Ramalingam, Fellow, Advanced Packaging, Xilinx
The first talk examines the current state of the art in hardware for deep learning, and highlights the architecture and trends for system-level hardware optimized for artificial intelligence applications. The following talk expands into the device-circuit interactions from finfet devices to devices for the 5nm node and beyond. Standard cell layouts, variability, and performance power area co-optimizations will also be discussed. The 3rd talk focuses on the scaling challenges and process/design interactions, especially circuit and chip level performance, power, density, functionality/yield and reliability co-optimizations. Another important area addressed is power devices and power management, which the 4th talk will focus on, covering the process needs of low voltage power management design and some of the key criteria to enable higher efficiency and lower cost. System-level 3D integration is the next important area to address the system-level scaling requirements. The 5th topic focuses on the key advanced packing enabling technologies for 2.5D/3D and system level integration.

8th Annual IEEE CPMT SCV Soft Error Rate (SER) Workshop 🗓 🗺

— tutorials, alpha upset, materials selection, process control, case studies …

Date: Thursday, November 3, 2016
Time: 9:30 am – 3:30 pm (Lunch will be provided)
Location: Juniper Networks, Building 6, 1215 Borregas Ave, Sunnyvale
Attendance: On-site or Remote (WebEx)
Cost: Free
Sponsors: IEEE CPMT Santa Clara Valley (SCV) Chapter, and Juniper Networks; Pure Technologies; Cisco Systems; XIA.

Our annual IEEE Soft Error Rate Workshop, now in its 8th year, focuses on alpha-induced soft errors with its unique offering of simultaneous on-site and remote participation. It provides opportunities for publication and interactive discussion on a variety of critical subjects on SER for an ever-increasing international audience.
This year’s event has a new format: We will be inviting industry experts in the field to offer three tutorials on fundamentals of alpha-related soft errors (shown in red below), to bring engineers and managers up to speed, interspersed with three presentations on current issues, solutions and case studies. Note that all times are Pacific Standard Time; please convert, for your location.
For those participating via WebEx on the Internet, we will send log-in information to all registrants on Wednesday, November 2nd.
See summaries of the contents of the tutorials and talks at this location.


Time (PST) Presenter Title
9:30 AM Check-in and Registration
10:00 AM Eric Crabill, Xilinx Tutorial: An Introduction to Single Event Effects (more)
10:45 AM Adrian Evans, iROC Tutorial: System Design Considerations for Soft Error Mitigation (more)
11:30 AM Rick Wong, Cisco Challenges of Alpha Testing (more)
12:00 Noon Lunch and Exhibits
1:00 PM Brendan McNelly, XIA; Mike Gordon, IBM Tutorial: Techniques and Challenges of Alpha Emissivity Measurements (more)
1:45 PM Laura Monroe, Los Alamos National Lab Resilience and Inexact Computing (more)
2:15 PM Francis Classe, Cypress Soft Error Upset Sensitivity to the Array Background Pattern in SLC Floating Gate and Charge Trapping Flash Memories (more)
2:45 PM Eric Crabill, Xilinx Alpha-Induced Soft Errors in Xilinx UltraScale+ Devices – Not a ‘Material’ Issue (more)
3:30 PM Close of Workshop

Workshop & Tabletop Expo: Flexible Hybrid Electronics — Opportunities and Challenges 🗓 🗺

Chapter Workshop (with the Consumer Electronics Chapter)

IEEE Santa Clara Valley CPMT Society Chapter Workshop (with the Consumer Electronics Chapter)
Speakers: see below
Organizers: Shomir Dighe, Chair; Annette Teng, Azmat Malik, Ralic Lo.
Workshop Date: Wednesday, September 21, 2016

  • Registration and continental breakfast: 8:00 AM
  • Call to Order and Welcome: 8:50 AM
  • First presentation: 9:00 AM
  • Lunch, demonstrations: 12:00 PM – 1:00 PM
  • Afternoon presentations: 1:00 PM – 3:30 PM
  • Reception/Networking: 3:30 PM – 4:15 PM
  • Closing: 4:30 PM

Cost: $45 IEEE members; $55 non-members; $25 students, unemployed

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara

Summary:The Workshop is targeted for engineers and managers contemplating entry into the Flexible Hybrid Electronics/Wearables market. It covers the challenges and opportunities in this emerging market. Development trends in the basic building blocks for products in this market will be covered. Experts will provide an overview of polymers, interconnects, sensors and energy sources along with producibility challenges for commercialization.
As a bonus, the workshop will feature product demos and an enlightening market survey followed by a raffle and a networking reception.
Expo: Representatives from a cross section of the Flexible Hybrid Electronics ecosystem as well as the platform developer community will be at tabletop expo that will be open during breaks and lunch.

Opening address/Overview: 9:00 AM (Malcolm Thompson, Executive Director, Next Flex)
9:30 AM: Polymers — Status and Future Developments (to be announced)
10:00 AM: Interconnects — Status and Future Developments (Janos Veres, Program Mgr for Printed Electronics, PARC)
10:40 AM: Flexible TFTs and Flexible Sensors (Arvind Kamath, VP-Technology Development, ThinFilm)
11:00 AM: Power Considerations Including Energy Harvesting (Brian Zahnstecher, PowerROX)
11:30 AM: Flexible Hybrid Electronics Circuit Design and Design Automation (Jim Huang, Research Scientist, HP Labs)
12:00 Noon: Lunch Break & Expo
1:00 PM: Manufacturing Challenges and Opportunities (Dan Gamota, VP-Strategic Capabilities Engng & Tech, Jabil)
1:30 PM: Flexible Display Electronics/Wearables Market (Sweta Dash, President, Dash-Insights)
2:15 PM: Product Demos (including live demo of Fuji Dimatix printer)
3:15 PM: Wrap up and Raffle Drawing
3:30 PM: Reception and Networking

IEEE Electronic Components and Technology Conference 🗓 🗺

— CPMT Society’s Flagship Conference …

— CPMT Society’s Flagship Conference …
Dates: May 31 – June 3, 2016
Location: Cosmopolitan Hotel, Las Vegas, NV
Summary: The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange.
— Information and Registration:
— Save $100 through May 5th.
— Download the Advance Program today.

IEEE InterSociety Thermal Conference 🗓 🗺

— CPMT Society’s Key Thermal Conference …

— CPMT Society’s Key Thermal Conference …
Dates: May 31 – June 3, 2016
Location: Cosmopolitan Hotel, Las Vegas, NV
Summary: The international conference for scientific and engineering exploration of thermal, thermomechanical and emerging technology issues associated with electronic devices, packages and systems.
— Information and Registration:
— Save $100 through May 5th.
— Download the Advance Program today.

Architecture and Design for the Internet of Things 🗓 🗺

— IoT Week in Silicon Valley: management, industrial IoT, Standards …

— IoT Week in Silicon Valley: management, industrial IoT, Standards …
Dates: June 6-10, 2016
Location: Santa Clara Convention Center, Santa Clara
— Mark your calendar for the week of June 6-10
— half a dozen IEEE events at the Santa Clara Convention Center
— one registration gains admittance to all sessions
— register for only one, then attend any/all!

Does your career require you to master the upcoming challenges of IoT? Then IEEE has you covered! Attend one or more:
— The IEEE Tech Industry Summit on IoT and exhibits (June 6, 7)
— The IEEE-IES Int’l Symposium on Industrial Electronics and industrial informatics (ISIE) (June 8, 9, 10)
— The IEEE-TEMS Technology and Business Challenges in IoT Deployment Workshop (June 8)
— plus standards meetings of the IEEE Internet of Things Committee and IEEE SCC 42 Transportation Standards Committee, and a Students and Young Professionals (S-YP) Forum.
Get more information, and register by April 20th: