Roll-to-roll Manufacturing in Electronics: Making it Work πŸ—“ πŸ—Ί

β€” charge-array, deposition, registration, evolution, flip-chip and TFTs …

β€”- NOTE CHANGE OF MEETING ROOM —
Speaker: Peter C Salmon, Salmon Engineering
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Presentation Slides: “Roll-to-roll Manufacturing in Electronics: Making it Work” (1 MB PDF)
Meeting Date: Tuesday, January 10, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members, students, unemployed; $10 non-members
Location: (Download MAP) Texas Instruments Building C, Big Sur Room, 3689 Kifer Rd, Santa Clara
Reservations: 1701cpmt.eventbrite.com


Summary:

Summary: A new concept for roll-to-roll fabrication is presented. A key component of each deposition station in the proposed roll-to-roll system is a charge-array wafer. The charge-array wafer enables two disruptive innovations: 1) “active registration” wherein the target substrate is continually seeking precise alignment, even as it moves through a deposition station; and 2) electronic programming of the desired pattern for each deposition layer.
A potential product evolution is described, beginning with flexible printed circuits (FPCs) having 1-mil line and space. Then FPCs with embedded passives, Hybrid Electronic Systems (HES) having attached flip chips, and finally complex electronic systems incorporating FPCs, embedded passives, flip chips, and thin-film transistors. The complex systems may include novel structures that are not currently found on PCBs.


Bio: Peter Salmon received his BE degree in Electrical Engineering from Auckland University, New Zealand. He emigrated to the United States and obtained MSEE and EE degrees at Northeastern University. He has enjoyed an eclectic career, including 10 years at Intel and Fairchild Semiconductor as a chip designer, 10 years at TRW and GTE as a systems engineer for large defense systems, almost 10 years founding startup companies involving thermal and electrostatic printing technologies, and a few more years as an engineering consultant and expert witness. He is a co-founder of i-Blades, Inc. which is pioneering new markets in attachments to smart phones; he developed the base technology for magnetic and electrical coupling. He has been awarded a first patent on his roll-to-roll technology, and a second one is pending.

8th Annual Soft Error Rate (SER) Workshop: Details

Below are summaries of each of the tutorials and talks. Return to this page following the Workshop to download PDFs of the slides.

Presenter Title Details
Eric Crabill, Xilinx Tutorial: An Introduction to Single Event Effects (SEE) This tutorial is a technical backgrounder on SEE in semiconductor devices, to establish a baseline understanding of origins, effects, mitigation, and testing. Key points made in this presentation are:
1. SEE have a relatively long history and can affect all semiconductor devices.
2. SEE arise from environmental radiation and present a variety of undesired behaviors.
3. SEE mitigation is possible and SEE susceptibility can be measured.
After this tutorial, attendees will have general familiarity with radiation effects in semiconductor devices. With this background, they will be primed for the other tutorials and presentations that follow during the day.
Adrian Evans, iROC Tutorial: System Design Considerations for Soft Error Mitigation This talk will discuss the system level impact of soft-errors. We will look at the factors that drive system level reliability requirements including standards such as ISO-26262 as well as pragmatic factors such as customer perception and product return rates. Then a methodology for analyzing the system-level impact of soft-errors will be presented. This consists of first enumerating the system level failure modes and then listing the sources of faults at the technology level, including RAMs, flip-flops, combinatorial logic and complex IPs. Finally, using de-rating factors, it will be shown how the rate of system-level failures can be estimated and how specific design techniques can be applied to improve reliability and availability.
Rick Wong, Cisco Challenges of Alpha Testing Alpha Testing on Semiconductors present several logistic challenges.
Accelerated testing with alpha sources
β€’ Obtaining radiation license and uniform alpha sources
β€’ Wire bond package, air and geometry
β€’ Component and system level testing
β€’ Calculation of SER, package and wafer alpha emission
Unaccelerated testing
β€’ Test facilities
Component and system level testing
12:00 Noon Lunch and Exhibits
Stuart Coleman, Brendan McNelly, XIA; Mike Gordon, IBM Tutorial: Techniques and Challenges of Alpha Emissivity Measurements In this tutorial we will discuss some techniques and the many challenges that occur when making accurate measurements of ultra-low alpha emissivity materials. Details of the operation of the XIA UltraLo-1800 detector will be given. Among other topics covered, we will discuss the sample measurement time as it relates to levels of detection, radon adsorption, detection efficiency, as well as measuring both non-metallic and irregularly shaped samples.
Laura Monroe, Los Alamos National Lab Resilience and Inexact Computing The rate of faults in hardware is expected to increase in coming years as a result of decreased feature size. We discuss inexact computing as a way of dealing with this.
Inexact computing includes the fields of probabilistic computing and approximate computing. A non-negligible rate of random faults on a device can be considered as a form of probabilistic computing. These faults introduce probabilistic error into calculations, which may be quantified and treated as a source of probabilistic variation in the calculation. Probabilistic computation is an emerging computational approach that calculates non-deterministically to attain a result that may be correct or β€œcorrect enough”. Approximate computation is a related field that produces results that are β€œclose enough” to a correct answer, because of precision limits or numeric methods.
We will discuss overlap between the fields of resilience and inexact computing, and how developments in one may lead to insights in the other.
Francis Classe, Cypress Soft Error Upset Sensitivity to the Array Background Pattern in SLC Floating Gate and Charge Trapping Flash Memories Data corruption and faults in electronics and memories due to Single Event Upset (SEU) has been studied variously by many authors, both in the terrestrial environment as well as in accelerated testing, such as from a neutron beam or a radioactive source placed in close proximity to the memory. The effect of SEU has been widely investigated on SRAMs, and neutron flux has been shown to vary strongly with altitude, on the order of several hundred times. However, data on Floating Gate and Charge Trapping flash memories is not quite as common and little attention has been paid to the impact of SEU sensitivity to the pattern programmed into the array of SLC flash memory. In this talk we will discuss the significant dependency of SEU on the pattern programmed into the device and the implications for the computation of SEU performance for a customer applications.
Eric Crabill, Xilinx Alpha-Induced Soft Errors in Xilinx UltraScale+ Devices – Not a ‘Material’ Issue Xilinx UltraScale+ Devices, fabricated with Xilinx 16nm FinFET technology, and assembled and packaged with premium ULA materials, has rendered alpha-induced soft errors immaterial. This result of applied science in product development is the result of close collaboration between component engineering and radiation effects teams.
3:30 PM Close of Workshop

Workshop & Tabletop Expo: Flexible Hybrid Electronics — Opportunities and Challenges πŸ—“ πŸ—Ί

Chapter Workshop (with the Consumer Electronics Chapter)

IEEE Santa Clara Valley CPMT Society Chapter Workshop (with the Consumer Electronics Chapter)
Speakers: see below
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Organizers: Shomir Dighe, Chair; Annette Teng, Azmat Malik, Ralic Lo.
Workshop Date: Wednesday, September 21, 2016

  • Registration and continental breakfast: 8:00 AM
  • Call to Order and Welcome: 8:50 AM
  • First presentation: 9:00 AM
  • Lunch, demonstrations: 12:00 PM – 1:00 PM
  • Afternoon presentations: 1:00 PM – 3:30 PM
  • Reception/Networking: 3:30 PM – 4:15 PM
  • Closing: 4:30 PM

Cost: $45 IEEE members; $55 non-members; $25 students, unemployed


Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1609wcpmt.eventbrite.com

Summary:The Workshop is targeted for engineers and managers contemplating entry into the Flexible Hybrid Electronics/Wearables market. It covers the challenges and opportunities in this emerging market. Development trends in the basic building blocks for products in this market will be covered. Experts will provide an overview of polymers, interconnects, sensors and energy sources along with producibility challenges for commercialization.
As a bonus, the workshop will feature product demos and an enlightening market survey followed by a raffle and a networking reception.
Expo: Representatives from a cross section of the Flexible Hybrid Electronics ecosystem as well as the platform developer community will be at tabletop expo that will be open during breaks and lunch.

Speakers:
Opening address/Overview: 9:00 AM (Malcolm Thompson, Executive Director, Next Flex)
9:30 AM: Polymers — Status and Future Developments (to be announced)
10:00 AM: Interconnects — Status and Future Developments (Janos Veres, Program Mgr for Printed Electronics, PARC)
10:40 AM: Flexible TFTs and Flexible Sensors (Arvind Kamath, VP-Technology Development, ThinFilm)
11:00 AM: Power Considerations Including Energy Harvesting (Brian Zahnstecher, PowerROX)
11:30 AM: Flexible Hybrid Electronics Circuit Design and Design Automation (Jim Huang, Research Scientist, HP Labs)
12:00 Noon: Lunch Break & Expo
1:00 PM: Manufacturing Challenges and Opportunities (Dan Gamota, VP-Strategic Capabilities Engng & Tech, Jabil)
1:30 PM: Flexible Display Electronics/Wearables Market (Sweta Dash, President, Dash-Insights)
2:15 PM: Product Demos (including live demo of Fuji Dimatix printer)
3:15 PM: Wrap up and Raffle Drawing
3:30 PM: Reception and Networking

Embedding and Miniaturization in Electronics Packaging πŸ—“ πŸ—Ί

β€” market needs, form-factors. wearables, cameras, consumer electronics, power converters …

β€” market needs, form-factors. wearables, cameras, consumer electronics, power converters …
Speaker: Wolfram Zotter, Sales Engineering, AT&S Americas LLC
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Presentation Slides: “Embedding and Miniaturization in Electronics Packaging” (1.6 MB PDF)
Meeting Date: Tuesday, August 9, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1608l1cpmt.eventbrite.com
Summary: Miniaturization is quite a topic these days but it’s far more than simply shrinking form-factors. Accommodating market needs featuring products like Wearables, Cameras, Consumer electronics, Power converters and many more applications require additional features such as solutions for form-factor, reliability, thermal needs and efficiency improvements. Within this talk we will see how embedding technology (ECP) can cater to those needs as well as why it can solve and help with individual and very specific needs.

Bio: Wolfram Zotter is currently heading the US Engineering group within AT&S Americas LLC. This group takes Field-application-engineering responsibilities and also involves in technology and solution promotion. Wolfram started at AT&S in 2002 responsible for production front-end, where he was able to gather basic know-how and experience. Later he was involved and lead teams within AT&S across multiple locations globally and made sure that market needs would be addressed with proper technologies. Since moving to the US in 2008 he has been heavily engaged with local OEMs as well as CEMs and ODMs.

Company tour of Jabil Blue Sky Design and Prototyping Center πŸ—“ πŸ—Ί

– digital prototyping, 3D printing, embedded sensors, UX design, printed electronics …

– digital prototyping, 3D printing, embedded sensors, UX design, printed electronics …
Host: Hien Ly, Jabil
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Meeting Date: Thursday, August 25, 2016
Time: 11:30 AM Registration and lunch (sandwiches/drinks); 12:00 – 1:00 PM small-group tours
Cost: $5 IEEE members, students, unemployed; $10 non-members
Location: Jabil Blue Sky, 6375 San Ignacio Ave., San Jose
Reservations: 1608lcpmt.eventbrite.com by August 11th
Summary: The Jabil Blue Sky Center was designed to help engineering growth and establish new markets in an environment of rapid change. At the forefront of Jabil’s technological effort, the Blue Sky Center displays some of the world’s cutting-edge technologies such as factory-of-the-future capabilities like automation, as well as product design, intelligent digital supply chain, the Internet of Things and more. The Jabil Blue Sky Center leverages collaborative spaces for creating, cultivating and incubating new ideas from vision to prototype to global manufacturing.

CMOS Biochips: The Good, the Bad, and the Hype πŸ—“ πŸ—Ί

– design, processes, manufacturing, packaging, biochemistry, applications …

– design, processes, manufacturing, packaging, biochemistry, applications …
Speaker: Arjang Hassibi, CEO, InSilixa
Meeting Date: Thursday, May 19, 2016
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Time: 6:00 PM Networking and Refreshments; 6:30 PM Presentation
Cost: none ($6 donation requested for food)

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Details and reservations: (URL)
Summary: In the past two decades, there have been numerous attempts to take advantage of semiconductor solutions (broadly defined) to create high-performance biosensors and bio-molecular detection devices. The goal has always been to create molecular diagnostics technologies that offer the cost efficiency, miniaturization capabilities, and manufacturing robustness of consumer electronics devices. The outcome so far has not been very exhilarating and unfortunately there have been few impactful products based on such efforts.
In this talk, we will discuss the use of CMOS processes and ICs for biotechnology in the form of integrated biochips. The focus will be not only on the design, manufacturing, and the packaging of biochips, but on the biochemistry and applications requirements. We will also discuss in detail a few implemented biochips that InSilixa is currently developing for commercialization in the nucleic acid (DNA/RNA) testing applications.

Increased Power Density and Simplified Designs with 3-D SiP Module πŸ—“ πŸ—Ί

β€” trade-offs, form-factor, functionality, flexible designs, real estate …

β€” trade-offs, form-factor, functionality, flexible designs, real estate …
Speaker: Jim Moss, Texas Instruments
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Sponsors: CPMT SCV Chapter, co-sponsored by PELS Chapter
Meeting Date: Thursday, July 28, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1607lcpmt.eventbrite.com
Summary: This talk will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules. It will provide more details on the SiP eco-system, co-design, construction, materials and circuit topology.
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more real estate toward end-user applications — all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required also. For example, in wearable products, the semiconductor industry has recently seen an increase in the use of system-in-package (SiP) technology for users who want simpler, more flexible designs and need to fulfill challenging space requirements. And, we expect to see this trend continue.

Bio: Jim Moss is the Power Products Technology Manager in TI’s Silicon Valley Analog. He is currently working on high-power modules utilizing controllers, MOS & GaN FETs, and passives. He has over 35 years of experience in the semiconductor industry and with TI/National for more than 25 years.
His experience covers Power, Wireless/RF, x86, and microcontrollers. He has been working in Systems Design, Product, Test and various technical management roles. He holds an MS-EM from Santa Clara University and BS-EE from Illinois Institute of Technology.

Advanced Packaging Techniques as Enablers for the Health IoT Ecosystem πŸ—“ πŸ—Ί

β€” health IoT, production processes, data capture, biocompatibility, packaging …
Speaker: Dr. Andreas Middendorf, Fraunhofer IZM
Meeting Date: Monday, January 25, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1601lcpmt.eventbrite.com
Summary:
The Internet of Things (IoT) is seen as a revolutionary step forward connecting the world. In today’s presentation, most of the scenarios revolve around the radical changes anticipated in how production processes are managed, how autonomously reacting systems for “Smart Cities” can be implemented and how business models will change when communication breaks down domain barriers between applications while using, augmenting and connecting existing data capture devices. The medical sector, however, will be affected in a twofold way. Not only can we expect that safety, security and decision making routines will see changes, but also novel sensors and man-adapted integration concepts are required to bring “Health IoT” to reality. Such a revolutionary health ecosystem will thus call for miniature, energy efficient, wirelessly connected microdevices which allow us to measure health related parameters, also in conjunction with ambient information and additional meta data. For a ubiquitous deployment, miniaturization is required with biocompatibility in mind, and also cost efficient manufacturing and a modular system concept is needed.
This talk offers insight on current state of the art of advanced packaging, the interface of these technologies towards system design and man-adapted integration concepts as well as the challenges to be overcome by research in the near future.


Bio: Andreas Middendorf studied electrical engineering at the Technical Universities of Aachen and Wuppertal where he specialized on information and communication technologies. He has been working as a scientist in the Environmental and Reliability Engineering department of the Fraunhofer Institute for Reliability and Microintegration (IZM) and of the Technical University Berlin since May 1995. He was responsible for the development and implementation of methods and demonstrators for the estimation of lifetime for electronic appliances.
Further on he is investigating technological aspects which combine the electronics design with environmental engineering techniques. This includes environmental assessments through LCA and through other methods, especially for Eco-Design, the evaluation of recycling attributes, the development of databases and software as well as environmental and safety oriented product evaluation.
Since 2010 until 2015 he was senior manager for the application field automotive and transportation systems and in charge of the System Reliability and Measurement Group at IZM. Andreas has since coordinated several cooperative research projects in Germany and Europe on technology reliability, safety and security. In 2015 he was appointed business developer in the Business Development Team of The Fraunhofer Institute for Reliability and Microintegration (IZM) and is addressing cross-domain aspects of Advanced Packaging and System Integration Technology.

FO-WLP – A Disruptive Technology: Drivers and Developments πŸ—“ πŸ—Ί

β€” smart phones, wafer-level packaging, fan-out, drivers, impact, trends …

β€” smart phones, wafer-level packaging, fan-out, drivers, impact, trends …
Speaker: E. Jan Vardaman, TechSearch International, Inc.
Presentation Slides: “FO-WLP – A Disruptive Technology: Drivers and Developments” (2 MB PDF)
Meeting Date: Tuesday, February 9, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1602lcpmt.eventbrite.com
Summary: Mobile devices, including smartphones, are driving package developments and unit volume growth in the semiconductor industry. Many companies have adopted wafer level packages (WLPs). WLP has seen strong growth, especially for mobile devices, because it provides a low-profile package that meets the low-profile packaging requirements of high-end smartphone makers. The introduction of fan-out WLP (FO-WLP) represents an additional change in the infrastructure. FO-WLP is a disruptive technology that will have a significant impact on the electronics industry in the coming years. WLP is disruptive technology because there is no substrate and thin-film metallization is used for interconnect instead of bumps or wires. This presentation examines the drivers for FO-WLP and the impact on the existing infrastructure. Applications and market trends are presented. Alternatives to the existing FO-WLP structures are described.

Bio: E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is a columnist with Printed Circuit Design & Fab/Circuits Assembly Magazine, is an IEEE CPMT distinguished lecturer, and the author of numerous publications on the microelectronics market and technology trends. She is a member of IEEE CPMT, IMAPS, SMTA, MEPTEC, and SEMI. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP πŸ—“ πŸ—Ί

β€” TC bonding, drivers, accuracy, platform, advanced processes …

β€” TC bonding, drivers, accuracy, platform, advanced processes …
Speaker: Tom Strothmann, Director, Advanced Packaging Next-Gen Products, Kulicke & Soffa Industries
Presentation Slides: “A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP “ (700 kB PDF)
Meeting Date: Thursday, February 25, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1602l2cpmt.eventbrite.com
Summary: Assembly with thermocompression bonding (TCB) enables the next generation fine pitch 2.5D and 3D products using Cu pillar interconnects, but the industry has been slow to invest in the dedicated infrastructure required for the process. TCB volume today is driven primarily by the memory market and stacked DRAM packages, including the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) products; however, the extreme placement accuracies required for TC bonding can be leveraged to enable improved capability for other assembly processes as well. With only minor modifications, the same equipment used for TCB assembly can also be used for highly accurate die placement in Fan-out Wafer Level Packages (FOWLP) and die placement for mass reflow processes with pitches as low as 30um. The flexibility inherent in new tool designs ensures cost effective HVM capability for TCB as well a manufacturing platform with the ability to adapt to product mix changes over time. The same tool purchased for Flip Chip or FOWLP die placement today can be configured to run HVM TCB 2.5D or 3D later. This presentation will review the performance of this flexible manufacturing platform over a range of Advanced Packaging processes.

Bio: Tom Strothmann is the Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major Asian OSATS. Tom has over 30 years of experience in semiconductor manufacturing, including extensive experience in both wafer fabrication and flip chip wafer level packaging.