A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP πŸ—“ πŸ—Ί

β€” TC bonding, drivers, accuracy, platform, advanced processes …

β€” TC bonding, drivers, accuracy, platform, advanced processes …
Speaker: Tom Strothmann, Director, Advanced Packaging Next-Gen Products, Kulicke & Soffa Industries
Presentation Slides: “A Flexible Manufacturing Platform for High-Volume TCB and High Density FOWLP “ (700 kB PDF)
Meeting Date: Thursday, February 25, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1602l2cpmt.eventbrite.com
Summary: Assembly with thermocompression bonding (TCB) enables the next generation fine pitch 2.5D and 3D products using Cu pillar interconnects, but the industry has been slow to invest in the dedicated infrastructure required for the process. TCB volume today is driven primarily by the memory market and stacked DRAM packages, including the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) products; however, the extreme placement accuracies required for TC bonding can be leveraged to enable improved capability for other assembly processes as well. With only minor modifications, the same equipment used for TCB assembly can also be used for highly accurate die placement in Fan-out Wafer Level Packages (FOWLP) and die placement for mass reflow processes with pitches as low as 30um. The flexibility inherent in new tool designs ensures cost effective HVM capability for TCB as well a manufacturing platform with the ability to adapt to product mix changes over time. The same tool purchased for Flip Chip or FOWLP die placement today can be configured to run HVM TCB 2.5D or 3D later. This presentation will review the performance of this flexible manufacturing platform over a range of Advanced Packaging processes.

Bio: Tom Strothmann is the Director for Advanced Packaging Next-Generation Products at Kulicke & Soffa Industries, Inc. Prior to joining K&S, Tom managed Wafer Level Products Business Development for STATS ChipPAC, including Fan-In and Fan-out WLP. Before STATS ChipPAC, Tom was Vice President of Business Development at FlipChip International and responsible for the formation of FlipChip Millennium Shanghai Co. At FlipChip Technologies, Tom successfully managed the transfer of bumping technology and the startup of bump lines for all major Asian OSATS. Tom has over 30 years of experience in semiconductor manufacturing, including extensive experience in both wafer fabrication and flip chip wafer level packaging.

Recent Advances and Trends in Semiconductor Packaging πŸ—“ πŸ—Ί

– fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …

– fan-out wafer/panel-level, 2.5D/3D, embedded, MEMS/IC integration …
Speaker: Dr. John H. Lau, Sr. Technical Advisor, ASM
Slides: Download here (3 MB PDF)
Date: Tuesday, April 12, 2016
Time: 11:300 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1604lcpmt.eventbrite.com
Summary: Recent advances in, for example, fan-out wafer/panel level packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, and 3D MEMS/IC integration are examined and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of fan-out wafer/panel-level will be discussed and some recommendations will be made.


Bio: John H. Lau has been a Sr. Technical Advisor of ASM since July 2014. Prior to that, he was a Senior Scientist/MTS at Hewlett-Packard/Agilent for more than 25 years. With more than 38 years of R&D and manufacturing experience, he has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 20 textbooks on, e.g., Reliability of RoHS compliant 2D and 3D IC Interconnects (2011), TSV for 3D Integration (2013), and 3D IC Integration and Packaging (2015). He is an IEEE Fellow and ASME Fellow.

Challenges and Opportunities of Circuits and Systems for the Internet of Things πŸ—“

– smart devices, data, cloud computing, sensor design …

– smart devices, data, cloud computing, sensor design …
CO-Sponsored by Circuits and Systems (CAS) Chapter
Speaker: Dr. Yen-Kuang Chen, Principal Engineer, Intel Corporation
Meeting Date: Wednesday, April 20, 2016
Time: 6:30 PM Networking/Light Dinner; 7:00 PM Presentation
Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA
Reservations: sites.ieee.org/scv-cas
Summary: This meeting discusses the technical trends and challenges of circuits and systems on Internet of Things. Rapid advancement of networking technologies together with extreme miniaturization of computing and communication devices enable a host of new and exciting applications and services that connect the physical and the computational worlds. In the future, digital sensing, communication, and processing capabilities will be ubiquitously embedded into everyday objects, turning them into the Internet of Things (IoT). In this new paradigm, smart devices will collect data, relay the information or context to each another, and process the information collaboratively using cloud computing and similar technologies. This paradigm shift creates numerous challenges and opportunities for engineering. For example, in the future, enormous numbers of sensors will be deployed. The costs of servicing such sensors will be a major concern. It is often almost impossible to replace sensor batteries once they are in the field. Therefore, one major challenge is low power sensor design, or designs which do not require a battery change over the lifetime of the sensor. For example, if a sensor is deployed on an animal for tracking purposes, the battery of the sensor should outlive the animal. This creates a demand for energy-efficient designs. This seminar will discuss the challenges and opportunities of circuits and systems on Internet of Things.

Bio: Dr. Yen-Kuang Chen is a Principal Engineer at Intel Corporation. His research areas span from emerging applications that can utilize the true potential of internet of things to computer architecture that can embrace emerging applications. He has 50+ US patents, 20+ pending patent applications, and 85+ technical publications. He is one of the key contributors to Supplemental Streaming SIMD Extension 3 and Advanced Vector Extension in Intel microprocessors. He has served as a program committee member of 50+ international conferences on Internet of Things, multimedia, video communication, image processing, VLSI circuits and systems, parallel processing, and software optimization. He is a steering committee member of IEEE Internet of Things Journal, the past-chair of Internet of Things special interest group of IEEE Signal Processing Society, and the Editor-in-Chief of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He received his Ph.D. degree from Princeton University and is an IEEE Fellow.

Package Requirements for High-Speed Systems πŸ—“ πŸ—Ί

β€” SiP solution, enabling technologies, applications, packaging, market segments …

β€” SiP solution, enabling technologies, applications, packaging, market segments …
Presentation Slides: “Package Requirements for High-Speed Systems” (3.7 MB PDF)
Speaker: Dr. Dongkai Shangguan, CMO, STATS ChipPAC
Meeting Date: Thursday, April 28, 2016
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: 1604l2.eventbrite.com
Summary: System-in-package (SiP) technology has been evolving through the utilization of various packaging technology building blocks to serve the market’s needs, with respect to miniaturization, heterogeneous integration, modularization, and smaller form factor, with the added benefits of lower cost and faster time to-market, as compared with SoC solutions. In this presentation, integration of advanced packaging technologies for the optimum SiP solution will be discussed, and enabling technologies for product solutions will be outlined for different applications and market segments.


Bio: Dr. Dongkai Shangguan is currently the Chief Marketing Officer of STATS ChipPAC, after having served as the Founding CEO of the National Center for Advanced Packaging Co., Ltd. (“NCAP China”). Previously, Dongkai worked for 10 years at the Electronics Operations with Ford Motor Co. in various technical and management functions, and for 11 years at Flextronics as Corporate Vice President of Global Advanced Technology and Engineering Leadership.
Dr. Shangguan, an IEEE Fellow, has served on the IEEE CPMT Society Board of Governors, the IPC Board of Directors, the Advisory Board of the Sustainable Electronics Manufacturing (SEM) Working Group, etc. Dongkai has received a number of recognitions for his contributions to the industry, including the “Outstanding Sustained Technical Contribution Award” from IEEE CPMT, “Leadership Award” from the Sustainable Electronics Manufacturing Working Group, “PresidentÒ€ℒs Award” from IPC, “Total Excellence in Electronics Manufacturing Award” from the Society of Manufacturing Engineers (SME), and the “Soldertec Lead-Free Soldering Award”.
Dongkai received his BS degree in Mechanical Engineering from Tsinghua University, China; Ph.D. degree in Materials from the University of Oxford, U.K.; and MBA degree from the San Jose State University. He conducted post-doctoral teaching and research at the University of Cambridge and The University of Alabama, and is currently a Guest Professor at several universities. Dr. Shangguan has published two books and authored/co-authored 250 technical papers and articles, and has over 20 patents issued.

Package Requirements for High-Speed Systems πŸ—“ πŸ—Ί

β€” SiP solution, enabling technologies, applications, packaging, market segments …

β€” SiP solution, enabling technologies, applications, packaging, market segments …
Speaker: Dr. Wendem T. Beyene, Rambus Inc.
Meeting Date: Tuesday, May 10, 2016
Presentation Slides: “Package Requirements for High-Speed Systems” (3 MB PDF) after meeting
Time: 11:30 AM Registration (and sandwiches/drinks); 12:00 PM Presentation
Presentation-only: 12:00 noon (come at 11:45)
Cost: $5 IEEE members. students, unemployed, $10 non-members

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara
Reservations: (URL)
Summary: As data rates increase rapidly in high speed systems — such as in SerDes and memory systems — to meet the bandwidth growth required by various applications, the electrical performance of packages has become critical. In addition, the role of new emerging 2.5D and 3D IC packaging platforms with ever-increasing system integration requirements have made the role of packaging even more important. The sources of signal loss, noise coupling and discontinuities in packages must be fully understood and minimized when designing packages. At the same time, the design and development of packages have to meet cost, performance, form factor and reliability goals. In this talk we will examine the key electrical characteristics: signal loss, signal crosstalk, return loss, mode conversion, power integrity and other important factors affecting the bandwidth of high-speed systems. These key performance metrics are discussed using measurement results from various package designs.


Bio: Wendem T. Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent Technologies. He is currently a technical director at Rambus Inc. where he is responsible for signal and power integrity of multi-gigabit serial and parallel interfaces.