Title:   "3-Dimensional Semiconductor Packaging and Integration"
with Charles E. Bauer, Ph.D., and Herbert J. Neuhaus, Ph.D., TechLead Corporation

Please Post and Circulate, through Oct. 1, 2007

LOCATION:
Holiday Inn San Jose
1740 North First Street, San Jose

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $300 for half-day Course; $450 for full day (2 Courses)
Non-Members: $350 for half-day Course, $500 for full day (2 Courses)
See descriptions of all 7 Courses in the Advance Program.
REGISTER at our on-line registration site, or use the printed Symposium Advance Program form.

OVERVIEW:
The latest trend in miniaturization of electronics systems, 3D packaging of both active and passive devices, opens a new world of performance and integration to system designers. This course covers both the fundamental and advanced technologies in use today to produce both stacked chip packages as well as stackable packages for implementation of highly integrated mobile electronic products. These include the challenges of die thinning, thin die attach, multi-level wire bonding, mixed technology die attachment and bonding, flip chip and TAB. Substrate selection for various 3D packaging techniques including silicon tiles, flex circuit origami and specialty interposers concludes the chip-stacking section of the course. Several examples of specific 3D package structures demonstrate both the power and limitations of these approaches.

Further considerations for 3D electronics include stackable packages based on flex and rigid substrate approaches, integrated system-in-package (SiP) techniques and multilayer, embedded passive technologies. The course concludes with a review of the drivers behind 3D packaging and presentation of multiple examples of 3D packages in actual usage today.

Course Outline:

• 3D Package Trends
• 3D Package Applications
• Drivers for 3D Packaging
• Stacked Packages
      Package on Package
      Origami
      Edge Stacked Modules
• Die Stacking
      Wire Bond
      Mixed Technology
      Edge Redistribution
      Through Silicon Vias
• 3D Integration (SiP)
• Issues in 3D Integration
• Intellectual Property Landscape for 3D Packaging

Intended Audience
Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging; electronic materials suppliers involved in materials manufacturing and research & development.

ABOUT THE INSTRUCTORS:

Charles E. Bauer, Ph.D. serves as Senior Managing Director of TechLead Corporation, a technology management company specializing in the electronics packaging, interconnection and assembly industry. Dr. Bauer focuses in the areas of strategic technology planning, market analysis and business development, primarily in the international arena. With more than 20 years experience spanning the range from printed circuit board and hybrid fabrication through complex IC metallization, multilayer packaging, multichip modules (MCMs) and flat panel display packaging and assembly, he brings tremendous breadth and depth to his work. Dr. Bauer lectures throughout the world on technology, business and market topics as well as serving on several corporate boards and international corporate, government and educational institution advisory councils. Chuck served ISHM as President of the NW Chapter, Technical Chair of the ISHM National Symposium in Seattle, National Technical Vice President of the Society and President of the Rocky Mountain Chapter. He founded the ISHM/IMAPS Advanced Technology Workshop program and served as General or Technical chair for several ATWs between 1990 and 1998. Dr. Bauer also served on the Board of Directors of the SMTA from 1997 through 2001 when elected President of IMAPS for 2001-2002. He now serves as Chair of the SMTA International Development Committee and remains active internationally with the SMTA, IEEE, IMAPS, JIEP and ASM.

Herbert J. Neuhaus, Ph.D. serves as Director of Operations of TechLead Corporation, where he supports clients throughout the world in the areas of intellectual property management and valuation as well as technical cost modeling and develops strategic planning tools. Active since 1980 in the development and characterization of electronic materials and associated manufacturing processes for a wide variety of applications including flip-chip for RFIDs and Smart Cards, LED assembly, chip interconnect and passivation, multichip modules, printed wiring boards, and flat panel displays, Dr. Neuhaus synthesized a unique perspective on electronics packaging, interconnection and assembly industry. Dr. Neuhaus received his Ph.D. degree in Physics from the Massachusetts Institute of Technology and holds the distinction of Fellow of the Society of the International Microelectronics and Packaging Society (IMAPS). He currently chairs the materials subcommittee of the IMAPS National Technical Committee and serves on the Board of Directors of Vyta Corp.