An IEEE Short Course in the S. F. Bay Area

Title:
"CHIP SCALE PACKAGING TECHNOLOGY FOR MODERN ELECTRONICS"
with Joseph Fjelstad

Please Post and Circulate, through Feb. 26, 2003

About This Short Course series
Course Overview
About the Instructor
How to Register

LOCATION:
UCSC Extension, 1180 Bordeaux Drive, Sunnyvale, near Highway 237 & Mathilda
Print out the map to the UCSC site.

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $225; Non-Members: $249
includes class handbook, lunch and refreshments.

INFORMATION:
Contact Dr. Bob Dubin (650-592-0315).

OVERVIEW:
This short course reviews basic design, construction, and performance aspects of selected chip scale packages (CSPs) in the marketplace now or under development. Key performance features of CSPs are compared and contrasted with the time-honored flip chip. The impact of chip scale devices on the design and manufacture of future interconnection structures is examined. Design standards now in development to facilitate market entry of chip scale technology will be reviewed and followed by a look at some innovative future options in IC package design.

WHO SHOULD ATTEND:
Design and electronic packaging engineers, project managers, purchasing managers, and others who influence future electronic packaging decisions in their companies. In addition, electronics industry suppliers of materials and processes who attend will better understand how to position their products as CSPs further press the limits of manufacturing technology.

TOPICS:

• Packaging Considerations in Electronics Assembly
• Chip Scale Package Offerings From Around The World
  • Peripheral CSPs, Area Array CSPs, Rigid and Flexible Interposers
• Performance Comparison Results of CSPs to Flip Chip
  • Electrical Modeling Comparisons, Reliability, Failure Analysis
• CSP Impact on Electronics Assembly
  • Testing, Handling, Assembly Processes, Wiring to Substrates
• Future Directions of IC Packaging
  • Packaging ICs On The Wafer; Fusing Package and Silicon

ABOUT THE INSTRUCTOR:
Joseph Fjelstad, a co-founder of startup Silicon Pipe, has been involved in the electronics interconnection industry for over 30 years in the development of manufacturing technologies for rigid and flexible PCBs and IC packaging, holding more than 70 US patents in the field. He has published numerous technical articles, several books on electronics manufacturing and interconnection technologies, and is regular columist for Circuitree and Global SMT and Packaging magazines.

HOW TO REGISTER:

         FEES:      IEEE Members:         $225  
                    other attendees:      $249
       (Includes class handbook, lunch, and refreshments)
  Checks or P.O.s should be made payable to "IEEE/CPMT"
  and sent with the completed registration form below to:
                    J. R. Technical Associates 
                    PO Box 5183
                    Belmont, CA 94002

HOW TO REGISTER:

Registration for IEEE Members ($225):
Registration for Non-Members ($249):

Limited Seating.  Register BY EMAIL NOW to reserve your seat!
Your registration will be CONFIRMED when payment is received.

--------------------------------------------------------------------------
                         REGISTRATION FORM
   CHIP SCALE PACKAGING TECHNOLOGY FOR MODERN ELECTRONICS 
               Wednesday, Feb. 26, 2003, Noon - 5 PM

  EMAIL your Registration Form to: myregistration@pacbell.net
    ---Copy to: jrtech@pacbell.net
    ---Include "C-2-26-03 REGISTRATION" in the Subject
    ---Send payment later
  Or: Call Dr. Bob Dubin for more Information: (650) 592-0315

  Mail Payment With A Copy Of Your Registration Form To:
  J.R. Technical Associates  PO Box 5183, Belmont, CA 94002
  Make Checks and Purchase Orders payable to "IEEE-CPMT".
  Payment due by 5PM Friday before class.  CHECKS PREFERRED.

NAME________________________   COMPANY________________________

ADDRESS__________________________ JOB TITLE___________________

CITY_____________________STATE__________ZIP____________________

Phone______________ Include FAX# for Confirmation______________

Email_______________________________________________

Manager's Name ___________________ Manager's Email: ___________

Payment by:
Check #_____________  P.O. #____________________  By PayPal___

Amount $________ IEEE# ________________ (Required For Discount)

              If you can't attend, what about a Team Member?
                                                        C-2-26-03