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An IEEE Short Course in the S. F. Bay Area

Title:   "Failure Modes and Analysis of Flip Chip Assemblies"
with Prof. Daniel Baldwin, Georgia Institute of Technology

Please Post and Circulate, through Oct. 1, 2007

DATE & TIME:
Wednesday, Oct 3, 2007, from 1:00 PM - 4:30 PM (lunch at noon)
(includes lunch and refreshments)

LOCATION:
Holiday Inn San Jose
1740 North First Street, San Jose

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $300 for half-day Course; $450 for full day (2 Courses)
Non-Members: $350 for half-day Course, $500 for full day (2 Courses)
See descriptions of all 7 Courses in the Advance Program.
REGISTER at our on-line registration site, or use the printed Symposium Advance Program form.

OVERVIEW:
Several material and process technology advances recently emerged for flip chip assembly processing such as fast-flow snap-cure underfills, no-flow underfills, emerging wafer scale underfills and associated innovative process technology. While a large number of technical publications help with understanding basic process requirements, understanding of failure modes and reliability standards remains essential for these technologies to gain traction in the industry. This course presents reliability test procedures, frequently encountered process defects and common failure modes that occur in flip chip packages and board level flip chip assemblies. The course focuses on accelerated reliability tests, process defect identification and resolution, failure mechanisms and the associated analysis tools needed to identify them such as FTIR, XRF, transmission X-ray analysis, acoustic microscopy and scanning electron microscopy. Descriptions of numerous process defects and failure modes presented along with extensive visual aids provide a more intuitive understanding of the defects and failure modes associated with these advanced assemblies. The course also discusses artifacts leading to process defects and how they contribute to premature failure.

Course Outline:

Intended Audience
Target audience includes individuals and companies associated with electronics packaging, particularly package reliability, failure analysis, and assembly process control/defects. The course should prove especially valuable to:

  • Managers: Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.
  • Engineers: Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who must solve process defect and packaging problems. Knowledge gained through this course will allow engineers and technologists to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.

    ABOUT THE INSTRUCTOR:
    Dr. Daniel Baldwin was a Member of the Technical Staff at Bell Laboratories before coming to Georgia Tech in 1995. He has a diverse research background, which provides a broad range of experience in manufacturing fundamentals and the engineering sciences. His early research was in assembly processes and assembly system design; he developed methodologies and software tools to aid in the design of assembly systems used to produce complex mechanical assemblies, such as automotive transmissions and engines. His research interests then expanded into the field of polymer processing, focusing on the system level design and development of new and innovative process technologies for the production of novel microcellular foam materials. Dr. Baldwin’s research expanded during his tenure at Bell Laboratories to work in electronics manufacturing, assembly, and packaging.

    Dr. Baldwin’s research focus includes low-cost manufacturing of next-generation electronic assemblies. Competitiveness in the global electronics industry demands that the next generation of electronic assemblies realize a ten-fold cost reduction over current practice, while increasing performance and functionality and decreasing size and weight. This research addresses these demands through the development of innovative materials and process technologies.

    He is active on smart tooling for the assembly of thin flexible systems. Here, emerging electronic assemblies demand lower cost, lighter weight, miniaturized packages mounted on thin, flexible circuit boards or flex circuits. This research seeks to develop such smart tooling for high-speed surface mount and high-volume packaging processes. He is also developing microelectromechanical systems (MEMS) and MEMS carriers for low-cost manufacturing.

    Dr. Baldwin’s research is sponsored by Siemens, the Defense Advanced Research Projects Agency, the National Science Foundation, Motorola, Chrysler, Cookson Electronics, Alpha Metals, Northrop Grumman, Loctite, and Georgia Tech.

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