An IEEE Short Course in the S. F. Bay Area

Title:
"Understanding Flip Chip Technology"
with Dr. Elke Zakel, PacTech, Germany

Please Post and Circulate, through July 18, 2001

About This Short Course series
Course Overview
About the Instructor
How to Register

LOCATION:
UCSC Extension, 1180 Bordeaux Drive, Sunnyvale, near Highway 237 & Mathilda

SPONSOR:
The Institute of Electrical and Electronics Engineers: the Components, Packaging, and Manufacturing Technology Society Chapter.

COST:
IEEE Members: $225; Non-Members: $249
includes class handbook, lunch and refreshments.

INFORMATION:
Contact Dr. Bob Dubin (650) 592-0315 or Dr. John Newman (408) 978-1069 (FAX# 408-978-1069)

OVERVIEW:
Flip Chip interconnect and packaging technology has significant advantages over wire bonding, especially in applications which require high performance and high leadcount. It has also been widely used for low cost, low lead count applications for many years. Flip Chip promises to be the interconnect and packaging technology choice in the future as designs become increasingly more demanding in terms of frequency and bandwidth. In this short course you will learn various aspects of Flip Chip Technology from an active "hands-on" industry expert. The class will cover different types of interconnect, underfill, and wafer bumping methods as well as assembly equipment and reliability considerations. The technical material presented in this class will improve your overall understanding of Flip Chip Technology and help you develop and achieve realistic Flip Chip design and manufacturing goals in your work.

WHO SHOULD ATTEND:
Packaging engineers, managers, marketing personnel. Design, process, failure analysis, and reliability personnel. Others involved in the design, development, and manufacturing of devices incorporating Flip Chip technologies.

TOPICS:

• Bumping Techniques For Flip Chip Assembly
  • Electroless Nickel, Solder and Stud Bumping
• Flip Chip Adhesive Interconnect Technology
  • Conductive Adhesives and Direct Chip Attach
• Quality and Reliability Issues
  • Known Good Die, Underfill Technologies
• Flip Chip Assembly Equipment Considerations
  • Manufacturing Issues
• Tradeoffs: Flip Chip vs Chip Scale
• Applications, New Developments, Future Trends

ABOUT THE INSTRUCTOR:
Dr. Elke Zakel is recognized as one of the leading authorities on flip chip technologies and has lectured and presented papers on this subject throughout Europe and the USA. She has worked extensively on the development of new chip interconnection technologies as well as the qualification of these techniques for industrial applications and is the author of numerous publications concerned with bonding techniques and reliability of flip chip, wire bond and TAB interconnections. Dr. Zakel holds M.S. and Ph.D. degrees in Materials Science from the Technical University of Berlin and is General Manager at PacTech where she is responsible for equipment, process, and package development of such technologies as electroless nickel bumping, laser bonding, and Chip Scale Packaging.

HOW TO REGISTER:

---------------------------- REGISTRATION FORM ----------------------------
               UNDERSTANDING FLIP CHIP TECHNOLOGY
                     Wednesday,July 18, 2001
Mail, Phone, or FAX  pre-registration to: J. R. Technical Associates
Mail to: J.R. Technical Associates  PO Box 5183, Belmont, CA 94002
Or: Ph./FAX to: (408) 978-1069
Or: EMAIL your Registration Form to: myregistration@pacbell.net
---Copy to: jrtech@pacbell.net
---Include "C-7-18-01 REGISTRATION" in the Subject.
Make Checks and Purchase Orders payable to "IEEE-CPMT".
CHECKS PREFERRED.
Sorry, we cannot accept credit card payments of any kind.

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