Title:
"Challenges and Approaches in Testing SoC Designs"
with Dr. Jacob El-Ziq

INFORMATION:
Contact our Course Registrar by email, or call 1-408-866-6516, for the course flyer.

OVERVIEW:

EE TIMES article: "SoC Test Reels Out of Control" -- System-level IC testing, already complicated by increasing chip capacity and the growing use of third-party intellectual property (IP), is now being threatened from another quarter. A proliferation of new failure modes being observed in very deep-submicron processes may force design managers and OEM executives to become directly involved in system test architecture at a level never before experienced by most companies.

As Moore's Law pushes device densities to over 100 million transistors per chip, and mixed-mode analog and digital designs are implemented, some design teams are now able to create full products on a single chip. Such designs combine an array of disparate "blocks", or subsystems, and bring all interconnect busses on-chip, for higher speed and lower power dissipation. The single-chip implementation should also be the lowest-cost way to achieve the product's function. Though this approach seems inevitable, there are a number of significant challenges affecting implementation. The major one at this time appears to be our ability to test these complex chips.

This 2-day course introduces the student to the field of SoC (System on Chip) DFT (Design For Testability) and ATPG (Automatic Test Pattern Generation). The course is divided into three parts: Test Synthesis, ATPG, and BIST (Built-In Self Test).

We first present the overall SoC design methodology. Both Logical and Physical Design flows are analyzed and then complemented with an overview of DFT (Design For Test) techniques, Test Synthesis, and tester interfaces. This includes detailed analysis of the industry’s leading DFT methodology called Scan Design.

In Part II, an overview of manufacturing test will be presented. Different types of failures that occur during the wafer’s manufacturing process will be discussed and the various leading fault models used to represent these failures will be covered. This includes the most popular Stuck-At fault model, the Path Delay model, and the IDDQ testing model. Next, we present how test vectors can be generated automatically using ATPG. The leading ATPG algorithms will be analyzed and we will show how they can be used to ensure high fault coverage for SoC devices under test.

The focus of Part III is on BIST -- the design methodology used to incorporate the tester into the device under test, allowing the device to test itself. BIST is gaining popularity in the SoC era because it saves considerably on the tester cost and also allows the device to be tested at high-speed. Both MBIST (Memory BIST) and LBIST (Logic BIST) techniques will be analyzed.

Finally, leading commercial CAD tools used to implement DFT, ATPG, and BIST functions will be presented.

WHO SHOULD ATTEND:
This course is intended for IC, ASIC and systems design engineers, software and hardware developers, test and QA engineers, and managers in development, QA, test, and manufacturing.

OUTLINE:

• Overall SoC Design Methodology
• Logical Design Methodology
• Physical Design Methodology
• DFT and Test Application Software
• Fault Modeling and Manufacturing Defects
• Scan Design: The Leading DFT Technology
• JTAG: Boundary Scan Design
• Fault Simulation
• ATPG (Automatic Test Pattern Generation)
• MBIST (Memory Built-In Self Test)
• LBIST (Logic Built-In Self Test)
• High Speed Testing Requirements
• Tester Interface Standards
• Commercial EDA Test Tools for SoC

ABOUT THE INSTRUCTOR:
Dr. Jacob El-Ziq, our instructor, received his Ph.D. from Utah State University in Computer Engineering. He is an ASIC design, verification, test and training specialist. He has over twenty years technical and management experience in both system and chip companies, including Honeywell, Unisys and Sun Microsystems on the system side, and Toshiba and VLSI technology on the chip side. His EDA experience includes five years managing DFT, ATPG and chip planning products at Synopsys, Inc. Dr. El-Ziq is also an adjunct professor at both Santa Clara University and San Jose State University, teaching courses on ASIC design, synthesis and test.

TO REGISTER: Please call our course registrar at 1-408-866-6516 to register; or register on-line at our website.