Components, Packaging & Manufacturing Technology Society

IEEE/CPMT One-Day Program:

"SYSTEMS-IN-PACKAGE (SiP) -- A New Dimension in Wafer Level Packaging" --
Exploring new, higher density, more heterogeneous IC packaging technologies

Co-sponsored by MEPTEC and CPMT/IEEE

(Download program and Registration Form: .doc, 50KB)
Wednesday, February 21, 2001
  • 9:00 AM - 5 PM
  • Cost: $150 ($125 for IEEE and MEPTEC members)

    Ramada Inn

  • 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.

    use the Registration Form.

    MEPTEC (Microelectronics Packaging and Test Engineering Council) and CPMT (Components, Packaging and Manufacturing Technology Society of IEEE) are joining forces to present a special one-day seminar on Systems-in-a-Package (SiP).

    In the July 2000 issue of ChipScale Review, Dr. Tom Di Stefano identified some of the rewards and challenges of wafer stacking as a value-added contribution to extending wafer-level packaging. Tom serves as moderator for this symposium that includes speakers who will address many of those rewards and challenges of stacking and other novel approaches to emerging new forms of Systems-in-Package.

    Lee Smith (Amkor) and Satya Chillara (ChipPAC) will present actual successful case histories. John Sovinsky (CAD Design Software) will discuss design techniques actually implemented. Martin Goetz (Alpine Microsystems) will discuss a high-density modular approach to Silicon-on-Silicon. There will be representatives from Irvine Sensors, Dense-Pac, Vertical Circuits, and others that are introducing new stacking technologies. The program will conclude with a panel discussion. Come and bring your questions to this focused event.

    Moderator: Dr. Tom DiStefano, President and CEO of DECISION TRACK

    Presentations will include:

    9:00 am - 9:30 am -- SiP-A New Dimension to Wafer Level Packaging
    Presented by Dr. Tom DiStefano, President and CEO, Decision Track
    Originally from IBM, Tom is the packaging innovator whose name is on most of Tessera's chip scale package patents. Wafer level packaging and its "new dimension", stacking, is a current interest. He will provide an insightful overview of the stacking issues-test, yield, die connection, wafer thinning, burn-in, logistics.

    9:30 am - 10:00 am -- Advancements, Trends and Applications in 3D and Thin Packaging Technologies
    Presented by Lee Smith, Director - New Product Development, Amkor Technology
    This presentation will address trends and applications driving packaging advancements in 3D (stacked chip and package stacking) and extremely thin packaging technologies. Focus will be on the trends and applications associated with wireless handsets that require higher levels of silicon efficiency to deliver continuous size, weight and cost reductions while delivering more features, functions and services.
    Advances in Stacked Chip Scale Packages, extremely thin packaging technologies, wafer level packaging technologies will be discussed as enabling technologies for innovative new handset form factors. Roadmaps and material requirements for 3D and extremely thin packaging technologies will be presented with a look to areas where further industry cooperation/infrastructure could benefit the electronics and semiconductor industries by driving wider availability and adoption of new packaging technologies.

    10:00 am - 10:30 am -- Silicon Based HDI for SiP Applications
    Martin Goetz, Director, Alpine Microsystems

    10:30 am - 10:45 am -- Break

    10:45 am - 11:15 am -- Advanced IC Packaging Technology for " System-in-Package"
    T. D. Her, Ph.D., Director of Packaging, Siliconware Precision Industries Co. Ltd.
    The ever-increasing demand of electronic system for more functions in smaller form factor, at higher speed, and lower cost has brought the semiconductor industry toward the next-level technology challenge. As System-On-a-Chip (SOC) is emerging to be the optimal solution, its implementation remains unclear. A SOC design usually involves various integrating IP's from many sources using different processes with mixed technologies. (i.e. 0.25 ?m CMOS process for core logic and 0.18?m process for memory combined with GaAs or SiGe technology for analogs.) Such technology challenges usually increases the design complexity, prolongs the product development time, and increases cost that cannot be justified by its performance. System-In-Package, (SIP), serves perfectly as an alternative solution to bridge the technology transition by enabling IP's with different processes, and mixed technologies all into a single package, using the state-of-the-arts advanced IC packaging technologies without impacting the IC chip designs.

    11:15 am - 11:45 am -- Stacked Die and 3D Bondwire Yield Rate Optimization
    Presented by John Sovinsky, CAD Design Software
    Die stacking is one of the most promising of the emerging chip scale packaging (CSP) techniques geared toward mobile phone markets. Typically found in CSP package formats of 8x8mm to 8x12mm with lead counts of less than 100 balls, this technology lends itself with relative ease into the memory market arena, particularly with SRAM and Flash products. By combining two or more die products together and coupling them with unique innovations in package design rules has allowed further package area reductions.
    Until now, optimization of the wire bonding process was done on the manufacturing floor by making adjustments to the wire bonder's machine program after the substrates and dies are delivered for assembly. Since the substrate design is completely finished by this time, many of the opportunities for improving packaging yield have passed.
    The ideal time to optimize the wire-bonding pattern is during the design process before the substrate is routed. This allows the designer to improve the design of the bond wire and substrate bond pad layout. For complex stacked die packaging, this may prove to be critical in enhancing yield.

    11:45 am - 1:00 pm -- Lunch (included in fee)

    1:00 pm - 1:30 pm -- Stacked Chip-Scale Packaging : Markets and Technology
    Presented by Satya Chillara, Director Strategic Marketing, BGA and CSP Products, ChipPAC, Inc.
    The presentation will discuss a review of semiconductor industry growth, in particular CSP growth rates. Also, reviewed are semiconductor stacked packaging trends, growth rates, and market applications. The focus of the paper is on the plethora of CSP solutions that are available in the industry and what makes sense for the subcontracting industry to make it available to the varied customer base to drive the adoption of certain package types.

    1:30 pm - 2:00 pm -- System in a Cube
    John Carson, Irvine Sensors

    2:00 pm - 2:30 pm -- FLEX-PAC -- Cost-effective 3D Packaging
    Andy Ross, Dense-Pac

    2:30 pm - 2:45 pm -- Break

    2:45 pm - 3:15 pm -- Vertical Stacking of IC Die
    Presented by Marc Robinson, VP Engineering & Operations, Vertical Circuits Incorporated (VCI)
    Dense packaging of integrated circuits is required for use in many of today's electronic products such as cellular phones, personal digital assistants, portable electronic systems, satellites, military avionics, and other portable systems. Deep submicron integrated circuit technology is enabling system-on-a-chip (SOC) capabilities for today's system designers. However, there are still situations that preclude the use of system on a chip technology. These arise from requirements for electrical noise isolation, RF isolation, or semiconductor process incompatibility resulting from subsystem integrated circuit process requirements. Vertical Circuits Inc. (VCI) technology allows designers to stack system components inside one package to provide a "system in a socket" capability. This stacked multichip package (MCP) technology uses a patented Vertical Interconnection Process (VIP) and/or Direct Contact Process (DCP). In some cases, a chip-scale package (CSP) containing stacked die can be smaller than if all functions were included on one integrated circuit die! VCI, a TRW affiliate company, was formed by the merger of Cubic Memory, Inc., and TRW Components International (TRWCI). VCI is focused on high density products for the mil/aerospace and commercial markets, and is manufacturing fully molded stacked die in unique and semi-standard BGA and TSOP packages.

    3:15 pm-3:45 pm -- Synergetic Effects of Wafer Thinning and 3D Stacking
    Sergey Savastiouk, Tru-Si Technologies
    Portable applications demand new and effective solutions for ultra-thin electronic devices and systems. Technologies that can provide both wafer level vertical miniaturization (wafer thinning) and preparation for 3D chip stacking (thru-silicon vias) in one step will make a difference in semiconductor industry. One of the industry's newest technologies, atmospheric downstream plasma (ADP), accomplishes in one step both thinning and opening thru-silicon vias. The natural etch-selectivity of the dry ADP chemical process allows for opening isolated buried metal vias to form thru-silicon backside contacts during selective maskless etching (backside wafer thinning). Moreover, a reduced removal-rate of isolation layers is compared to silicon, to the extent that an over-etch cannot possibly degrade the isolation. Neither grinding nor wet etching as current thinning techniques can achieve such important technological effects. The presentation will discuss the synergetic effects of the ADP use for 3D chip stacking.

    3:45 pm - 5:00 pm -- PANEL DISCUSSION

    If you are not on our Chapter's regular email or FAX distribution list for meeting anouncements, you can easily be added! Please send an Email to Tom Tarter and let me know if you'd like email or FAX distribution. If you don't have Email, then please reply to 800 686-9366 (CPMT's 800 number), but please be advised that I would greatly prefer the Email route.

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    Revised 29 January 2001