San Jose Convention Center (see map). Plan to attend WESCON that afternoon (free admission), then stop by our meeting for dinner and the talks.
PLEASE RESERVE IN ADVANCE --
On Wednesday October 17 at 6 PM, the Santa Clara Valley section of the
Components, Packaging, and Manufacturing Technology Society will present a
special program at the San Jose Convention Center, Room B4 on the exhibit
level in conjunction with the WESCON Exposition and Conference.
The venue and times will change for this special event from the usual Ramada Sunnyvale location. For those who come at 5:15, there will be free pizza, soft drinks, and socializing, courtesy of WESCON. WESCON/2001 Exhibit hours that day are 10 AM to 5 PM. The Conference hours are 9 AM to 5 PM and include many papers related to electronic packaging, manufacturing, and test. Here are several of high interest in packaging:
"The SQUEEZE Is On! Designing Sockets for Next-Generation IC Packages". Ron Iscoff, Editor of "Chip Scale Review", chose this title for his article on CSP Sockets in the April 2001 issue of the magazine. Ron then summarized the gist of the article by saying "Shrinking IC packages, with their increasingly tighter pitches, make CSP socket design a complex task, demanding a unit that works reliably up to a million times". We couldn't have said it any better.
The High-Density sockets that Gabe Cherian has designed and is developing address this exact issue. They could have been called "CSP sockets", as well. These sockets are designed based on a technology that can be extended to "Probes" and other similar interconnection devices. He calls it "Parallel Nesting" of springs, together with the use of "Combs", to create and control wipe and/or scrub.
In this presentation, He will explain the underlying technology and how it has been applied to create High-Density sockets and probes. The sockets can be used for test and burn-in due to their ruggedness. They can also be used for production due to their low cost. Several versions of probes will also be shown, including some that can test more than one chip at a time.
Furthermore, the sockets and the probes, together with their combs, are designed to counteract the effect of TCE mismatch during thermal cycling. And he will also show how the technology can be applied to other innovative concepts, such as those developed by "FormFactor".
is an engineer who has worked for over 25 years with connectors, interconnection devices and electronic components. He has 21 basic patents, 13 of them are on such products. He worked 7 years with AMP Incorporated, Harrisburg, PA and 17 years with Raychem Corporation, Menlo Park, CA. Interestingly enough, TYCO International acquired both companies in 1999.
A couple of years ago, Gabe started to develop, on his own, under the name of "Cherian Enterprises", some new products for the electronics industry. Now he has two product families ready for the market. They are based on a technology platform where springs and needles are arranged in a certain fashion, working in conjunction with "combs". They can then be used as High-Density Sockets, Probes and the like.
Gabe will tell us about these products.
Gabe served as Chairman of the Santa Clara Valley CPMT Chapter, for 3 years, from 1982 through 1985. He then served as Secretary & Treasurer for a couple more years. He then served as Program Chairman for the five following years, when he organized plant tours, seminars and courses, such as the "Electronics for Non-Electronic Professionals". Another program was the "Electronic Manufacturing Technology" series. This covered all the complete processes needed to make a computer or an equivalent electronic system, starting from the Silicon base material, all the way up to the finished product. Gabe was on the Advisory Board of Directors of the CPMT Chapter for thirteen consecutive years.
Gabe served also as the Education Chairman for the Santa Clara Valley Section of the IEEE. He was Co-Chairman of the Tutorial Committee of WESCON 1987 in San Francisco. At one time, Gabe was on a "JEDEC" committee and on a SEMI Packaging Task Force.
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