Components, Packaging & Manufacturing Technology Society

IEEE/CPMT Dinner Meeting:

Plating Processes for IC and Microelectronic Interconnect Applications --
William Sepp, Technic Inc.

Wednesday, November 14, 2001
  • Seated dinner served at 6:30 ($20 if reserved before Nov. 10); $25 after & at door; vegetarian available)
  • Presentation (no cost) at 7:30.

    Ramada Inn

  • 1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.

    PLEASE RESERVE IN ADVANCE --

  • For dinner and/or meeting: by email to Tom Tarter
  • or call our CPMT hotline at 1-650-299-8898.
  • Please reserve for "presentation-only", even if not attending the dinner.

    OVERVIEW:
    The metallization and interconnect technology used in IC and microelectronic manufacturing has borrowed extensively from the production processes developed for electronic components and printed wiring boards. Many of today's microelectronic plating processes for nickel and gold are the same as those previously used in other industries. Tin lead electrolytes for wafer bump have been adapted for application specific equipment. Acid copper electrolytes for copper Damascene have been modified to suit both the equipment and the scale of features to be plated. Finally, new formulations including low alpha lead, gold-tin and nickel-cobalt have been developed for specific interconnect applications, bonding techniques and MEMS manufacturing.

    Speaker Biography
    William Sepp began his career in field of electroplating 27 years ago manufacturing automotive and aerospace relays. The next fifteen years working for a major chemical supplier were spent developing plating applications for the manufacture of printed wiring boards. Mr. Sepp has been a senior staff engineer assigned to semiconductor division of Technic Inc., Anaheim, CA for the past eight years. His current activities include; the integration of chemical processes in automatic manufacturing equipment with emphasis on process monitoring and control. Development and characterization of lead free finishes for printed wiring boards and electronic components. Optimization of buried and blind via technologies for high density interconnects and electroplating methods and equipment for wafer level metallization and bumping.
    If you are not on our Chapter's regular email distribution list for meeting anouncements, you can easily be added! Please send an Email to Paul Wesling and let me know if you'd like email or FAX distribution. If you don't have Email, then please reply to 800 686-9366 (CPMT's 800 number), but please be advised that I would greatly prefer the Email route.

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