IEEE/CPMT Dinner Meeting:
Wafer Level Packaging --
Wednesday, February 13, 2002
Dr. Luu Nguyen, Package Technology Group, National Semiconductor Corp.
(PDF file of talk -- 1.2MB)
Seated dinner served at 6:30
($20 if reserved before Feb. 9); $25 after & at door;
Presentation (no cost) at 7:30.
Ramada Inn1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
PLEASE RESERVE IN ADVANCE --
For dinner and/or meeting: by email to
or call our CPMT hotline at 1-650-299-8898.
Please reserve for "presentation-only", even if not attending the dinner.
A Wafer Level Package (WLP) is the product of the complete packaging of a component at the wafer level. A true WLP utilizes materials and equipment that process all the dies on the wafer simultaneously for all the process steps. The package does not depend on the fabrication of non-semiconductor layers such as flex films or the individual placement and connection of features. Masks and other tooling consistent with standard semiconductor processing are used, ensuring rapid turns on both new designs and adaptability to die shrinks. Low lead count packages and integrated passive RF components based on WLP technologies are already turning up in today's hand held telecom products. This talk will review the need for WLP, the current production processes, the reliability characterization (package and board level reliability), and the challenges (materials, processing, and tests) facing WLP adoption.
- Speaker Biography
- Dr. Luu T. Nguyen is a Senior Engineering Manager in the Package Technology Group at National Semiconductor Corp., working on various aspects of wafer level packaging, opto packaging, lead-free, thermal measurement and modeling, and design-for-manufacturability. He is also in charge of external leveraging with the government, industry consortia, and research universities. He obtained his Ph.D. in Mech. Eng. from MIT on a Hertz Foundation Fellowship, and has worked for IBM Research (Yorktown Heights, NY) and Philips Research (Sunnyvale, CA). He has co-edited 2 books on packaging, and has over 40 patents and invention disclosures, and over 160 publications. He is an IEEE Fellow, and is currently an Associate Editor for the CPMT Transactions on Advanced Packaging, an Editorial Board Member for the Journal of Electronics Manufacturing, and the Chair of IEEE TC-18 on Wafer Level Packaging.
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