IEEE/CPMT Dinner Meeting, in the Santa Clara Valley:
"MultiLayer Ceramic Capacitor (MLCC) Value Drift"
-- Dr. Daniel N. Donahoe, Exponent Inc,
-- Dr. Nicholas Biunno, Sanmina-SCI
Presentation Slides: "Impedance Characterization and Design Optimization of PCB Embedded Passive Components" (1 MB PDF) and "Drift (due to Moisture) in Multilayer Ceramic Capacitors" (700 kB PDF)
Wednesday, February 8, 2006 Seated dinner served at 6:30
($25 if reserved before Feb. 5; $30 after & at door;
Presentation (no cost) at 7:30.
$25 -- Register & prepay for dinner in one step from your PayPal account or Credit/Debit Card!
Ramada Inn1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
PLEASE RESERVE IN ADVANCE --
For dinner and/or meeting: by email to
Please reserve for "presentation-only", even if not attending the dinner.
"MultiLayer Ceramic Capacitor (MLCC) Value Drift"
As IC progress drives more functionality onto each IC, fewer ICs are typically
placed on each PCB. In addition to this trend, ever-increasing operating frequencies and
lower IC voltages require more passive components. As a result, the multilayer ceramic
capacitor (MLCC) has become the most common component used in digital electronics.
The capacitor industry has not stood still while the IC industry moved forward.
MLCCs have continued to shrink in size, primarily to satisfy the requirements driven by
modern handheld products such as cell phones. In addition, an almost 10 times market
spike in the price of palladium (electrodes were made of silver and palladium are called
precious metal capacitors) forced the industry to transition to nickel electrodes. The use
of nickel electrodes in a MLCC is termed base metal electrodes (BME). Today, most
MLCCs are BME.
Humidity testing for both precious metal electrode and base metal electrode
(BME) capacitors showed that the precious metal capacitors aged according to a well
known aging mechanism, but the BME capacitors degraded to below the failure criterion
at 500 hours of exposure. The reasons for this new failure mechanism are complex. This
talk will outline the testing and provide a theory why this degradation was witnessed.
Standard testing protocols will likely not uncover this problem.
The trend in digital circuit design is for higher speeds. For example, high speed chip-to-chip and board-to-board interconnects are being designed for data rates in excess of 12.5 Gb/s. At these speeds surface mount discrete passive components can approach or exceed their limits of operation and current design practices must adopt new techniques to enable future high-speed digital systems. Printed circuit boards with embedded passive components, (resistors, capacitors and inductors) offer many advantages to application design and circuit functionality. These advantages include improved signal integrity, increased functionality, reduced system cost and higher reliability.
This talk discusses the impedance characteristics of printed circuit board embedded resistors and capacitors. Consideration is given to the effects on impedance for a given geometric design. S-parameters are extracted in the frequency range from 0.1 to 20 GHz. Where possible we attempt to compare circuit designs using 0603 and 0402 surface mount resistors and capacitors to equivalent circuits with embedded resistors and capacitors. Modeling parameters are derived and compared to measurement results. From collected data and modeling results we show how embedded passives may be designed in to optimize circuit speed, bandwidth and signal integrity.
A robust embedded passive process requires a repeatability that can maintain nominal resistor and capacitor values and at the same time maintain the tolerance required by the circuit application. Also in high speed design any change to a passives geometry by trimming to tolerance may have a negative effect on the high frequency impedance response. We will discuss methods of trimming resistors (planar vs. slice cut) and compare the effects.
We summarize and conclude with the ABC's of embedded passive enablement:
A. Embedded passive part characterization - S-parameters are characterized for a given part shape and type.
B. Design implementation - an overview of current design tools for embedded passive designs.
C. Design for Manufacturability - overviews high yield, high reliability and cost effective embedded technologies.
- Speaker Biographyies:
Dr. Daniel N. Donahoe is a Managing Engineer in Exponentís Mechanical Engineering and
Materials/Metallurgy practice. Dr. Donahoe has over two decades of industrial experience
working with defense electronics and commercial electronics. Prior to joining Exponent, he has
been employed at Lockheed, Motorola, Ford Aerospace, Teledyne, Compaq Computer and
Iomega, and the University of Marylandís industry and government sponsored CALCE
Electronic Products, and Systems Center. His functional assignments include work as a design
engineer, reliability engineer, thermal engineer, manager, technologist, and scientist. In military
electronics he worked on electronics exposed to extreme environments ranging from the high
acceleration loads of gun launch to thermal challenges faced in life support and the design of
radar systems. In addition to electronic products exposed to exotic environments, he has
worked on cost-driven commercial electronics products such as cooling of computer
components. He has worked on integrating rack and stacked electronics into facilities,
especially focusing on the design of HVAC (Heating, Ventilation and Air Conditioning). His
electronic packaging analysis skills include thermal analysis, stress and dynamics analysis and
failure analysis. His Ph.D. dissertation on ceramic capacitors included failure analysis work
using modern tools of failure analysis including the environmental scanning electron
microscope (ESEMô), electron backscatter diffraction (EBSD) and focused ion beam (FIB).
Dr. Donahoe has worked on several industry standards related to electronics. He has also served
as an Associate Editor of the IEEE Transactions on Components and Packaging Technologies
for seven years.
Dr. Nicholas Biunno is a Principal Scientist for the PCB Division of Sanmina-SCI.
He received a Ph.D. in Materials Science and Engineering from North Carolina State University in 1989. He has worked at ALCOA Electronic Packaging Corporation in new product development (flip chip assembly and failure analysis) prior to joining Zycon Corporation. He has been with Zycon, now Sanmina-SCI Corporation, for more then 11 years. In that time he has worked on various projects including integrative passives and failure analysis of solder joint surface finishes. Nicholas has authored 30 publications and 3 US patent in electronic materials processing and characterization. He is a member of CPMT's Technical Committee on
Discrete and Integral Passives.
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