IEEE/CPMT Luncheon Meeting, in the Santa Clara Valley:
"3-D and Multi-Technology Packaging: Current Capabilities"
Presentation Slides: "3-D and Multi-Technology Packaging: Current Capabilities" (700 kB PDF)
-- Phil Marcoux, CORWIL
Thursday, September 28, 2006 Buffet lunch served from 11:45 - 12:15
($15 if reserved by Sept 25; $20 at door;
vegetarian available); presentation at 12:15.
Register & Prepay for lunch ($15) in one step from your PayPal account or Credit Card!
1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
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John Jackson, Analog Devices
The interest in multi-component (MCP) IC packaging has created several new assembly technologies and demands. The nuances of some of these technologies are well understood for some and emerging daily for others. This presentation will summarize what is known and is still challenging for the key technologies including wafer thinning, dicing before grid, die stacking, new die-attach materials, wire bonding and flip chip. The speaker will cover the common substrate types, the economics, and the design challenges encountered though his company's experiences.
- Speaker Biography
Phil Marcoux is a Senior Member of the IEEE and past Executive Director of MEPTEC. He's currently the SIP/MCP and Business Development Manager for CORWIL (Milpitas CA). Previously Phil was CEO of two well-known start-ups and Associate Professor at the Graduate School of Engineering, University of Santa Clara.
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