IEEE/CPMT Luncheon Meeting, in the Santa Clara Valley:
"3-D and Multi-Technology Packaging: Current Capabilities"
-- Phil Marcoux, CORWIL
Presentation Slides: "3-D and Multi-Technology Packaging: Current Capabilities" (700 kB PDF)
Thursday, September 28, 2006
Buffet lunch served from 11:45 - 12:15
($15 if reserved by Sept 25; $20 at door;
vegetarian available); presentation at 12:15.
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Register & Prepay for lunch ($15) in one step from your PayPal account or Credit Card!
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Ramada Inn
1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
PLEASE RESERVE IN ADVANCE --
If you pay using our PayPal link, you are automatically registered for the lunch and meeting
Otherwise, for lunch and meeting, pre-register by email to
John Jackson, Analog Devices
- OVERVIEW:
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The interest in multi-component (MCP) IC packaging has created several new assembly technologies and demands. The nuances of some of these technologies are well understood for some and emerging daily for others. This presentation will summarize what is known and is still challenging for the key technologies including wafer thinning, dicing before grid, die stacking, new die-attach materials, wire bonding and flip chip. The speaker will cover the common substrate types, the economics, and the design challenges encountered though his company's experiences.
- Speaker Biography
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Phil Marcoux is a Senior Member of the IEEE and past Executive Director of MEPTEC. He's currently the SIP/MCP and Business Development Manager for CORWIL (Milpitas CA). Previously Phil was CEO of two well-known start-ups and Associate Professor at the Graduate School of Engineering, University of Santa Clara.
If you are not on our Chapter's regular email distribution list
for meeting anouncements, you can easily be added!
Please send an Email to
Paul Wesling
and let me know if you'd like email distribution.
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