IEEE/CPMT Dinner Meeting, in the Santa Clara Valley:
"Board Level Reliability of Wafer Level Chip Scale Packages with Copper Post Technology"
-- John Jackson, Packaging Development Manager, Analog Devices Inc.
Presentation Slides: "Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology" (450 kB PDF)
Wednesday, December 13, 2006 Seated dinner served at 6:30
($25 if reserved before December 10; $30 after & at door;
Presentation (no cost) at 7:30.
$25 -- Register & prepay for dinner in one step from your PayPal account or Credit/Debit Card!
Ramada Inn1217 Wildwood Ave (Fwy 101 frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale, (800) 888-3899 -- see map.
PLEASE RESERVE IN ADVANCE --
For dinner and/or meeting: by email to
Please reserve for "presentation-only", even if not attending the dinner.
Thermal cycling performance of Wafer-Level Chip-Scale Packaging (WLCSP) depends on many factors: board design, assembly process and the bump process. The typical failure mode observed for this package is fracture between die and solder bump interface. To strengthen the base of the solder ball during thermal cycling, an electroplated copper post was embedded on the RDL and encapsulated in a low-stress molding compound. The post increases the standoff, which enhances reliability. Evaluations were conducted on daisy chained units of a 41 I/O die, which is redistributed from the peripheral-pad 6 x 7 array of 250um-size balls at 450um pitch with Cu post. An array of this size requires underfill; effect of underfill and the type of material were included on this study.
Reliability performance was measured in accordance with IPC-9701. Thermal cycling from -40 to +125C was performed for a one-hour cycle with 15-minute ramps and 15-minute dwell times. Time-to-failure, plotted as a Weibull distribution, will be used to illustrate interesting and significant differences.
At time zero, the daisy chain resistance tracked with resistivity and trace width of copper and aluminum. Underfill did not change these values. Underfill selection had a significant effect on performance. Without underfill, copper redistribution metallurgy is preferred over aluminum. With underfill, the difference is not significant. Cu width may be a significant variable on the solder joint performance of WLCSP with Cu post.
Additionally, stress measurements and their effect on WLCSP design will be discussed.
- Speaker Biography:
John Jackson of Analog Devices has served on the AdCom for the local CPMT Society Chapter for the past 6 years, most recently as co-program chair for the luncheon meetings.
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