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OVERVIEW:

Increasing demand for graphical virtual reality and computation speed on gaming devices is pushing the process units from current 90nm into 65nm transistor sizes. To make a stride in reducing the problem of power leakage and improving the core performance in clock cycle, a new chip design strategy and process technology are required.

In this study, a product-specific technical consortium was initiated by voluntary participants, including OEM, Chip Supplier, Soldering Material and Fab Supplier, EMS, and Metallurgical/Failure Analytical Lab to study FCBGA thermal and mechanical reliability. A 65nm FCBGA with electrical daisy chain and thermal die was included in a Test Vehicle (TV) and Box Emulator (BE). To facilitate and streamline the design development cycle, a closed loop Design for Reliability model was used.

Finite Element Analysis was performed on a test board with almost the same probing pinout to see the strain response on the PCB by correlating to gage measurement. Then the strain level of the solder joint was benchmarked to the yield strength. The reliability of FCBGA-solder-PCB pad interconnect system will be real-time monitored during Accelerated Thermal Cycling (ATC) in order to assess the interconnect fatigue life and failure mode. In order to derive the mechanical residual stress correlation to the reliability scale, a four-point bending test fixture will be used to apply levels of stress before ATC is conducted on the stressed interconnect system. Finite Element Modeling will be performed to study the strain level in the solder interconnect to provide insights for fatigue life estimation. Extensive metallurgical analyses will be conducted at time zero as well as during the ATC to reveal solder crack growth, intermetallic compound evolution and interfacial grain structure.

The thermal interconnect management system, Process Unit-Thermal Interface Material-Heatsink-Fan, contained in the Box Emulator, is used to derive the die junction temperature (Tj) and thermal resistance (Rth) at various interconnect interfaces. Thermal degradation of the system, particularly the Thermal Interface Material (TIM), is also assessed by thermally stressing the system in ATC then plotting the Tj and Rth variation in time series.

Speaker Biography

Dr. Paul P.E. Wang received his Ph.D degree in Mechanical/Materials Engineering and his MBA in Management Science from State University of New York at Buffalo. Paul has published more than 60 technical papers in Journal of Material Science, Journal of SMTA and Circuits Assembly, and SMT, and also in the proceedings of SMTA, NEPCON, IPC APEX, Pan Pacific Microelectronics conferences and company internal websites. Paul and teams received Best of Conference Paper Awards in 2003 SMTA and 2005 IPC Apex. Paul is serving in iNEMI as co-chair for the Lead-Free Wave Soldering project as well as technical chairman for the Pan Pacific conference from 2005 to 2007 and IEEE Advanced Packaging Materials Symposium (APM'07) as Program Chair.

Paul is currently working in the Reliability Engineering Group in XBOX at Microsoft as Sr. Staff Reliability Engineer. He is responsible for hardware quality and reliability studies from electronic package, device, solder interconnection, to system levels.