IEEE Santa Clara Valley CPMT Society Chapter
"Nanopackaging: Nanotechnologies in Microelectronics Packaging"
-- James E. Morris, Department of Electrical & Computer Engineering, Portland State University
Presentation Slides: "Nanopackaging: Nanotechnologies in Microelectronics Packaging" (2 MB PDF)
WEDNESDAY, November 11, 2009
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:30 PM
($25 if reserved by Nov. 9 ; $30 after & at door;
- Presentation (no cost) at 7:30 PM.
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Please reserve for "presentation-only", even if not attending the dinner. We want to assure we have enough seating.
2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
While the electronics industry continues to look for the next nanoscale device to take over from the MOSFET, other nanotechnologies are already being developed for microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes (CNTs.) Composite materials are applicable to all the passive components, (high-k dielectrics, cermet resistors, inductors, and antennas), electromagnetic interference shielding, electrically conductive adhesives, dispensable conductive interconnect "inks," underfill fillers, and solder enhancement. CNTs find a similar range of applications within composites, but also as thermal and electrical interfaces. There are other nanoscale structures with great packaging potential, and all of these technologies offer new challenges for effective computer modeling, while new nanoscale modeling techniques provide the tools to understand old effects in new ways. Little work seems to be going on, however, on the packaging requirements of the nanoelectronics technologies of the future.
- Speaker Biography:
Jim Morris is an ECE Professor at Portland State University, Oregon, and Professor Emeritus at SUNY-Binghamton, having served as Department Chair at both, and is an IEEE Fellow. He has B.Sc. and M.Sc. degrees in Physics from the University of Auckland, NZ, and a Ph.D. in EE from the University of Saskatchewan, Canada, and was the first Director of Binghamton's Institute for Research in Electronics Packaging. Jim has served the IEEE CPMT Society as Treasurer (1991-1997), BoG member (1996-1998), VP for Conferences (1998-2003), Distinguished Lecturer (2000- ), CPT-Transactions Associate-Editor (1998- ), IEEE Nanotechnology Council representative (2007- ), etc., and won the 2005 CPMT David Feldman Outstanding Contribution Award. He has edited four books on electronics packaging, including one published last year on Nanopackaging, established the Nanotechnology Council Nanopackaging TC, and contributes to IEEE Nanotechnology magazine. He was General Conference Chair of Adhesives in Electronics (1998), Advanced Packaging Materials (2001), and Polytronic (2004). His research is currently focused on ECAs, nanoelectronics, and nanoelectronics packaging. He is actively involved in international engineering education, was founding chair of the IEEE Education Society's Oregon Chapter, and has spent the past year in visiting positions with the University of Greenwich, Chalmers University of Technology, Dresden University of Technology, Helsinki University of Technology (with a Nokia-Fulbright Fellowship), and the University of Canterbury, New Zealand (on an Erskine Fellowship).
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