IEEE Santa Clara Valley CPMT Society Chapter, with the Electromagnetic Compatibility Chapter

"Novel Fine Pitch, Low Profile, Low Cost Connector Technology" -- David Light, VP Technology, Neoconix, Inc.

• Buffet dinner served at 6:00 PM ($20 if reserved by June 7; $10 for fulltime students and currently unemployed engineers; $25 after & at door; vegetarian available)

• Presentation (no cost) at 6:45 PM

  Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the Doubleknot link above.
• Please reserve for "presentation-only", even if not attending the dinner. We want to assure we have enough seating.
Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW:

      This talk will present a revolutionary connector technology providing unparalleled design flexibility at low cost. A photolithographic approach to connector definition coupled with batch, printed circuit manufacturing methods allows highly configurable designs. Pin-out modifications, electrical performance tuning, tailoring of mechanical characteristics, and even adjustment of connector thickness can be accomplished quickly and easily with CAD modifications to low cost photo-masks and/or by modifications to the bill of materials. Connectors can be custom designed and fully optimized for each revision or generation of a product, with minimal tooling costs and lead time. Lithographically defined contact arrays also enable high levels of integration and miniaturization — pitch is no longer limited by the practical limitations of injection molding connector housings into which free standing spring contacts are subsequently stitched. Neoconix utilizes a MEMS process model, implemented using the low-cost printed circuit substrate infrastructure, to fabricate contact arrays that can scale with advances in photo-lithography and HDI printed circuit substrate technology.
      The connector fabrication process starts by defining arrays of copper alloy beams, in sheet format, in their ultimate configuration using large format, batch lithography and etch methods. The arrays of beams, still in sheet format, are then formed into three dimensional, 'S'-shaped cantilever beams, using low cost, programmable dies. The sheets of contact arrays are subsequently integrated into connector 'interposer' structures using standard printed circuit fabrication processes, including lamination, plating, and etching. The resulting one or two sided contact arrays can function as freestanding interposers or are readily integrated into standardized, low cost connector housings that provide alignment, attachment and actuation.
      This talk will review basic elements of the Neoconix PCBeam technology, and will use real-world applications as well as simulations to describe recent learning on the relative impact of the flexible design elements on signal integrity and bandwidth, mechanical characteristics, durability, contact resistance, and reliability, and will describe applications where system level designs have been improved from a functional, form factor and/or cost perspective by implementing Neoconix interconnect structures.

  Speaker Biography:
  

      David Light is Vice President, Technology at Neoconix, Inc. Prior to joining Neoconix in September, 2009, he was an independent consultant in providing ongoing and project-based services in technology development, intellectual property evaluation, business strategy, and technology marketing to clients including Tessera, Samtec, Flint Hills Solutions, Microconnex, Coleman Research Group, Latham and Watkins, and Neoconix, in areas spanning microelectronics packaging, high density substrates, and surface mount technology. His career has included fundamental process and materials R&D, process and product development, technology management, marketing and business development, manufacturing operations, and General Management. His areas of expertise include substrates and printed circuits, semiconductor packages (including assembly, test and burn-in), interconnect technologies, test tooling, and miniaturized electronic systems. David’s career began at the IBM T.J. Watson Research Center, in the electrochemical studies group, and has included technology and business leadership positions at IBM Microelectronics, Tessera, Flex2Chip, and Sunright/KES Systems.
      David is a graduate of Stanford University. He has over three dozen issued US patents and has authored numerous technical publications and presentations. He is a member of IEEE CPMT.

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