IEEE/CPMT Luncheon Meeting, in the Santa Clara Valley:
"Design of High Density & 3D Packaging: Tools and Knowledge"
Presentation Slides: "Design of High Density & 3D Packaging: Tools and Knowledge" Thomas S. Tarter, Package Science Services LLC (1.1 MB PDF)
-- Thomas Tarter, Package Science Services LLC
Thursday, September 23, 2010 Registration at 11:30 AM; Buffet lunch served from 11:45 - 12:15
($15 if reserved by Oct. 26; $5 for fulltime students and currently unemployed; $5 more at door;
vegetarian available); presentation (no cost) at 12:15.
Packaging of complex silicon devices requires a deep knowledge of many aspects of high-technology engineering disciplines. As an example, packaging a high lead-count chip requires knowledge of electrical, thermal, mechanical, chemical and manufacturing engineering. These disciplines must be known and must be used in the conceptualization, design and implementation of any package design. Complex systems many times require more than one die in the package. These chips can be stacked or arrayed onto a substrate to increase functionality and reduce size and cost, driving the complexity of the package beyond the capability of simple drawings and 2D design tools. 3D packaging creates challenges in the characterization and validation of thermal, electrical and mechanical functionality. This presentation provides an overview of package design for high-density, 3D products with a focus on the electrical characterization challenges. The talk will cover approaches for parameter extraction, high-frequency modeling and simulation and the need for advances and features in 3D design programs, and will go over a typical design flow for high-performance package development and implementation.
- Speaker Biography:
Thomas S. Tarter is an expert on thermal management, thermal and electrical characterization, and design of microelectronic and optoelectronic packaging structures. He spent 17 years at AMD in package characterization and was a Senior Member of the Technical Staff. Subsequently he was Director of BGA Package Engineering and Design at Advanced Interconnect Technology, and Principal Engineer for thermal management, temperature control and package development at NeoPhotonics Corporation, Inc. In 2009, Tom started Package Science Services LLC, to serve the high-tech community with electronic packaging expertise in design, analysis, and characterization (electrical, thermal, reliability) and support all phases of IC, solar cell, LED and other chip packaging from concept to hand off to mass manufacturing. Tom has published 30 papers, holds 5 patents, and has presented numerous short courses and lectures. He chaired the JEDEC JC15.1 task group on thermal standards for five years, was general chair of SEMI-THERM, Technical Chair for five years, and serves on the SEMI-THERM executive committee to date. Tom is a senior member of IEEE and was chair of the IEEE Santa Clara Valley Chapter of CPMT for two years. Society affiliations include, IEEE, LEOS, Santa Clara Valley Nanotechnology Council, MEPTEC, IMAPS, and SPIE.
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