IEEE Santa Clara Valley CPMT Society Chapter
"All-Silicon System with Nano-Packaging: Highest Functionality, Lowest Cost, Smallest Size"
-- Prof. Rao Tummala, Founding Director, NSF Packaging Research Center, Georgia Tech
Presentation Slides: "All-Silicon System with Nano-Packaging: Highest Functionality, Lowest Cost, Smallest Size" (1.3 MB PDF)
TUESDAY, October 12, 2010
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:00 PM
($20 if reserved by Oct. 9; $10 for fulltime students and currently unemployed engineers; $5 more after & at door;
- Presentation (no cost) at 6:45 PM
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Please reserve for "presentation-only", even if not attending the dinner. We want to assure we have enough seating.
- 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
Nanopackaging has been defined as the process of interconnecting, powering, cooling, and protecting the nanocomponents made of nanomaterials to form electronic and bioelectronic systems for greatly improved functionality and cost. In spite of Si CMOS-based active devices at 32 nm with a billion transistors, today's systems are limited by bulky, milliscale components that make up 90% of the system. In addition, the future of Si CMOS beyond 22 nm seems uncertain and the industry has shifted its R&D investments to three-dimensional (3D) ICs with through-silicon vias (TSVs). But 2D and 3-D ICs are a small part of any system, and the functionality per unit volume of the system can only be improved dramatically by miniaturization of non-active system components as shown in the illustration (click to enlarge =====>>).
The X axis represents the progress in Si CMOS-based devices; the Y axis represents the expected progress in 3-D ICs, not only in CMOS but also in heterogeneous ICs; and the Z axis represents Georgia Tech's 3D nanopackaging approach to miniaturize the entire system. The focus of the Z axis for the entire system is with nanoscale passives, thermal interfaces, batteries, and interconnections, all of which are being integrated into highly miniaturized systems leading to unparalleled miniaturization, functionality, and cost. Such an approach with nanoscale-active devices and nanoscale system components can lead to an all-silicon systems platform.
This presentation focuses on a variety of nanoscale materials, processes, and components to enable such a vision.
Consider attending Rao Tummala's afternoon Seminar, from 3:30 - 5:30 PM, then staying for dinner and this evening talk.
- Speaker Biography:
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF PRC at Georgia Tech, the largest Academic Center in Microsystems pioneering the System-On-Package (SOP) vision, since 1994. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage.
He has received many industry, academic and professional society awards including Industry Week's award for improving U.S. competitiveness, IEEE's David Sarnoff, Major Education and Sustained Technical Contribution awards, the Dan Hughes award from IMAPS, Engineering Materials Achievement award from DVM and ASM-International, Total Excellence in Manufacturing award from SME, John Jeppson's award from the American Ceramic Society as well as the Distinguished Alumni Awards from the University of lllinois, the Indian Institute of Science, Bangalore and Georgia Tech. He received his BS from IISc, Bangalore and his Ph.D. from the University of lllinois.
Prof. Tummala has published 426 technical papers, holds 74 patents and inventions; authored the first modern packaging reference book Microelectronics Packaging Handbook (Van Nostrand, 1988), the first undergrad textbook Fundamentals of Microsystems Packaging (McGraw Hill, 2001) and the first book introducing System-On-Package technology. He is a Fellow of the IEEE, IMAPS, and the American Ceramic Society, and member of the National Academy of Engineering in the USA and in India. He has served as President of both the IEEE-CPMT and IMAPS Societies.
If you are not on our Chapter's regular email distribution list
for meeting anouncements, you can easily be added!
Place yourself on our email distribution list [or send a request to
Last updated on