IEEE Santa Clara Valley CPMT Society Chapter, with the Electromagnetic Compatibility Chapter
"Embedded Passives: Packaging Paradigm of the Future?"
-- Jason Ferguson, Crane Naval Surface Warfare Center
Presentation Slides: "Embedded Passives: Packaging Paradigm of the Future?" (1.4 MB PDF)
WEDNESDAY, November 10, 2010
PLEASE RESERVE IN ADVANCE --
- Buffet dinner served at 6:00 PM
($20 if reserved by Nov. 9; $10 for fulltime students and currently unemployed engineers; $25 after & at door;
- Presentation (no cost) at 6:45 PM
Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.
You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.
- For dinner and/or meeting: at the Doubleknot link above.
- Please reserve for "presentation-only", even if not attending the dinner. We want to assure we have enough seating.
- 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.
Embedded Passive (EP) Technology is of interest to many OEMs and designers, but the technology remains a mystery for how and when to implement this technology into designs.
Embedded passives will be the next pivotal technology for PCBs. Simply stated, embedded passives are the incorporation (embedding or burying) of passive components, particularly resistors and capacitors, in a substrate. Around in some form for years, EPs are now seen as a key enabling technology in the National Electronics Manufacturing Initiative (iNEMI) Roadmap. The EP revolution is soon to come.
This presentation will reveal what EP materials are out on the market, what the benefits are for using the technology, and give examples of when implementation is viable to a design.
- Speaker Biography:
Jason Ferguson holds a Bachelor of Science degree from Rose-Hulman Institute of Technology. In 1995, he began a four year tour of duty as a commissioned officer in the U.S. Army. After his service, he went to work for the Naval Surface Warfare Center at Crane, IN. For the past ten years, he has served as a systems engineer on an air defense program called Cooperative Engagement Capability and as a process engineer for the printed circuit board (PCB) fabrication shop. For the past six years, he has been fabricating and testing embedded passive technology in PCB's. This has led to a project with the Jet Propulsion Lab at Cal Tech to embed resistors and capacitors into a current motor controller design to demonstrate electrical and reliability performance.
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