IEEE Santa Clara Valley CPMT Society Chapter

"Low Cost, Small Footprint Die Stacking and Interconnect for 3D Package Integration" -- Marc Robinson, Vice President & CTO, Vertical Circuits Inc.

• Buffet dinner served at 6:00 PM ($20 if reserved by March 7); $10 for fulltime students and currently unemployed engineers; $5 more at the door; vegetarian available)

• Presentation (no cost) at 6:45 PM

  Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the Doubleknot link above.
• Please reserve for "presentation-only", even if not attending the dinner. We want to assure we have enough seating.
Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW:

      By now, most of us have read about the promise of TSV (through silicon via) and the myriad of applications, mostly portable and low power, that are expected to benefit from 3D TSV solutions. While TSV does have the potential to address and abate the relentless drive for continued feature size reduction, it still requires investment in significantly expensive capital equipment to achieve its promise of increased functionality in a smaller footprint.
      Vertical Circuits (VCI) has developed an alternative packaging based solution to 3D integration that does not require significant capital expenditures, yet provides low cost, high volume manufacturing capabilities The technology focuses on the ability to insulate critical die surfaces, and the formation of conformal conductors over those surfaces to interconnect multiple, stacked die. VCI's core competency is the use of dispensable conductors for multi die packaging (flash, DRAM, MCP, MEMS, etc.), and the integration of materials to meet reliability and cost requirements for multi die high volume commercial applications. Although VCI initially focused the technology on stacking memory die, it has broad applicability for multi die packaging.
      Mr. Robinson will review the path VCI took in the development of this technology as it sought to support the increasing breadth of applications for the technology, review the benefits of using an assembly-based approach for high-volume production, and update us on the latest work VCI is doing to maximize reliability and yield as it ramps this technology for large, commercial applications.

  Speaker Biography:
  

      Marc Robinson is Vice President and CTO, for Vertical Circuits Inc., where he currently focuses on IP (intellectual property) strategy, analysis, assessment, and protection. He joined Cubic Memory, the predecessor to VCI, in 1996, as Vice President of Engineering and Operations. Before joining VCI, Mr. Robinson served as Vice President, Technology Development and Quality for Sierra Semiconductor. Prior to Sierra, he was Vice President of Engineering, and Vice President of TQM and Quality at GEC Plessey Semiconductors, and he served as a Business Unit Director at International Microelectronics Products (IMP). Mr. Robinson holds a BS degree in Physics from The Cooper Union, and an MS degree in Physics from Franklin & Marshall. Marc has extensive experience in the semiconductor industry, having held positions in business development, manufacturing, process engineering, and product and process design and development.

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