IEEE Santa Clara Valley CPMT Society Chapter

"New Class of Low-k Dielectrics for Advanced Interconnects" -- Yusuke Matsuda, Materials Science and Engineering, Stanford University

WEDNESDAY, January 9, 2013

• Buffet dinner served at 6:00 PM ($20 if reserved by Jan 7th) ; $10 for fulltime students and currently unemployed engineers
  ($5 more at the door; vegetarian available)

• Presentation (no cost) at 6:45 PM (arrive by 6:35 PM)

  Please register in advance for this event, using our IEEE Council's DoubleKnot registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the Doubleknot link above.
• Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW:

      Low-k dielectrics in microelectronic interconnects play a crucial role in increasing device performance and lowering power consumption. Silica-based low-k dielectrics are fragile, and have low device yield in packaging and limited reliability from cohesive or interfacial fracture caused by thermo-mechanical and packaging stresses in the interconnect structures. This is further aggravated in reactive environments like moisture or CMP slurries. These issues may be addressed by replacing Si-O-Si bonds with less reactive molecular networks to dramatically increase device reliability.
      Here, I present new silicon carbide-based low-k dielectrics containing no Si-O-Si bonds. These can be processed using available techniques, and exhibit excellent and widely tunable thermo-mechanical properties, as well as significant reduction of moisture-assisted cracking. These dielectrics can replace traditional silica-based low-k dielectrics in advanced interconnects, leading to a better damage tolerance, increased reliability and yield during packaging, chip stacking and TSVs processes.

  Speaker Biography:
  

      Yusuke Matsuda is a PhD candidate in the department of materials science and engineering at Stanford University. He received his bachelor's and master's degrees from Tohoku University, Japan. Before joining Stanford University, he worked as a reliability engineer in the R&D division at Hitachi Global Storage Technologies. His current research interests are the mechanical properties of advanced materials from hybrid materials to nanocomposites to nanolaminates for emerging nanoscience and energy applications. Dr Matsuda is a recipient of the IEEE CPMT-SCV graduate grant for Fall 2012.

  
  

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