IEEE Santa Clara Valley CPMT Society Chapter

"Inkjet Printing for Advanced Semiconductor Packaging: Pillars and TSVs"
Jake Sadie, Ph.D. Candidate, EECS - University of California - Berkeley
and "Improved PoP Package Competes with 2.5/3D Packages using TSVs"
Dev Gupta, PhD, CTO, APSTL llc

WEDNESDAY, June 11, 2014

• Buffet dinner served at 6:00 PM ($25 for IEEE Members, $30 for non-members, if reserved by June 9th) ; $10 for fulltime students and currently unemployed engineers
  ($5 more at the door; vegetarian available)

• Presentation (no cost) at 6:30 PM (arrive by 6:15 PM)

  Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

  You may register yourself, plus others from your company/institution, for both dinner and presentation, or for only the presentation. You may make an on-line payment for the dinner, or arrange to pay at the door.

PLEASE RESERVE IN ADVANCE --
• For dinner and/or meeting: at the EventBrite link above.
• Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:45 PM.
Biltmore Hotel

• 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara, (408) 346-4620 -- click map at right.

  
  

  OVERVIEW: Talk A

      As integrated circuits continue to scale and interest in new, thin form factors continues to grow, electrical interconnects and back-end-of-line (BEOL) packaging technologies are becoming an increasingly critical factor in overall chip performance. Improving material performance, implementing chip stacking, and decreasing overall costs are three primary drivers for next-generation packaging schemes, and inkjet printing of metal nanopartices is uniquely positioned to deliver on all three fronts. Due to their high surface area-to-volume ratio, encapsulated metal nanoparticles exhibit dramatically reduced melting points, enabling low-temperature sintering processes that result in high-conductivity structures. However, most nanoparticle-based fabrication has been confined to two-dimensional thin films rather than three-dimensional structures relevant to the packaging industry. To this end, we explore the necessary processing conditions and ultimate structural properties of two three-dimensional, nanoparticle-based structures: pillars and through-silicon vias (TSVs).
      In this talk, we will first explore inkjet printing processes for the fabrication of three-dimensional structures using gold nanoparticles and demonstrate the key process parameters required for freestanding pillar fabrication and TSV filling. Next, we consider the sinter-dependent material properties (electrical, elastic, and shear) for pillars and TSVs. Using heat treatments which do not exceed conventional BEOL process temperatures, it is possible to achieve printed structures with properties that outperform conventional packaging materials and approach bulk gold properties. We use custom four-point probe techniques, nanoindentation, solder bump shear testing, and focused ion beam with a goal of understanding the sintering processes for our inherently thick-film, nanoparticle-based structures. Finally, we discuss manufacturability of this process with respect to uniformity, yield, and the inherent systems constraints imposed by inkjet-driven processes.

  Speaker Biography:
  

      Jacob Sadie participated in nanotechnology- and semiconductor fabrication-focused research programs at the Georgia Institute of Technology and the Forschungzentrum – Juelich in Germany in 2009 and 2010, respectively. His work at Berkeley has focused on packaging applications and process development for inkjet-printed metal nanoparticles as well as studies on the formulation of colloidal inkjet inks.
      Jacob was awarded the James L. Edwards, Philip Prince, and Presidential Scholarships from Clemson University. He has recently earned Outstanding Student Paper and Best of Track Paper Awards at the IMAPS International Microelectronics Assembly and Packaging Conferences in 2012 and 2013, respectively, for his work on inkjet-printed packaging applications. He received his B.S. in Electrical Engineering from Clemson University in 2010. Jacob will earn his Ph.D. in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 2015.

  OVERVIEW: Talk B

      The industry has been awaiting maturation of 3D packaging technologies as a low-cost alternative to further integration. So far die stacking and interconnecting with Through Silicon Vias (TSVs) have received most attention.
      The adoption of 3D TSVs for manufacturing has been limited to cases where its use has resulted in performance benefits and reduced costs, e,g. BSI modules used in some Smart Phones. Cost reduction (by reduced yield losses) has been a key factor in the adoption of 2.5D for small-scale production of high-end FPGAs built as a multi-chip module rather than a single large chip. Such cost reduction has not yet been possible for CPU-Memory combinations in 3D stacks.
      This is not simply because of the high initial cost or supply-chain issues typical of new technologies, but also due to unresolved issues related to choice of material and process flow for 3D TSVs. These concerns, along with stress and thermal issues that affect device performance in 3D stacks, will be discussed.
      Lower-risk alternatives that can be implemented even in consumer systems e.g. Smart Phones are evaluated. To identify "low hanging fruit" analyses was carried out to simulate bandwidth and power needed to transfer data in 3D stacks and 2.5D modules using TSVs as well as several packages that do not use TSVs for application to Smart Phones.
      PoP (poor man's 3D) are ubiquitous in Smart Phones. APSTL project to improve electrical performance e,g. power efficiency (battery life) and bandwidth (video rate) of PoP packages will be described. Improved performance of the resulting Super PoP will be discussed and contrasted with other industry efforts to improve the PoP package.

  Speaker Biography:
  

      Dr. Dev Gupta has been innovating and pioneering Advanced Packaging technologies such as various types of Flip Chip (electroplated solder bump, pillar and micro-pillar bump, organic substrates, bonding robots) at Motorola and Intel that have now become industry standards. At Intel Dr. Gupta's Team succeeded in dramatically improving the yield and reliability of Organic Substrates, thus enabling the widespread adoption of flip chip technology. At APSTL he is responsible for development and licensing of new packaging technologies e,g. turnkey engineering of advanced packaging incl. bumping and substrate fabs and assembly, and now the "Super PoP" technology he will discuss in his talk.

  
  

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