IEEE Santa Clara Valley CPMT Society Chapter, with the SCV Reliability Chapter

"A New Drop Test for BGA Assemblies: Duplicable and Effective"
Dongji Xie, Nvidia

• 5:45 PM: Registration and Networking; pizza or sandwich with $5 prepayment on registration site.
• 6:30 PM: Presentation (no cost)

  Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

  You may register yourself, plus others from your company/institution, for both light dinner and presentation, or for only the presentation. YPlease make an on-line payment for the dinner.

PLEASE RESERVE IN ADVANCE --
• For networking/food and/or meeting: at the EventBrite link above.
• Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by 6:30 PM.
Texas Instruments Building E Conference Center

• 2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.

  OVERVIEW:

      The drop test per JEDEC standard (JESD22B111) has been widely used for evaluating the mechanical reliability of solder joints of BGAs for more than a decade. In JESD22B111, a rectangular board, 3"x5", with 15 BGAs has been employed as the test vehicle (TV). Because those 15 components have to be divided into 6 subgroups according to their stress levels, this requires a large sample size and a large number of drops in order to get statistically meaningful results. Due to the nature of the drop test, the variation of drop cycles to failure is normally much greater than other types of fatigue test such as bending and thermal cycling. This makes the current drop-test method very ineffective and inefficient. A second shortcoming for this standard is that only two parameters -- acceleration and drop duration -- have been defined, which may be not sufficient. Some experimental studies demonstrated that number of drops to failure would be significantly different for the same units but tested in two test labs even though they are tested using the same drop test parameters. The gap is even larger if using different drop testers. That is because the drop test setup is controlled not only by the peak acceleration and shock duration but also by the pulse shape and energy consumption.
      To solve the non-uniformity issue using rectangular boards per JESD22B111, a new TV using 3"x3" and 1mm thick is proposed, and assembled using a 12x12mm² BGA package. In this TV, 4 BGAs are mounted orthogonally with the same distance to the board center so that all inner and outer corner solder joints of all 4 BGAs are at the same stress level respectively during the drop test. To validate the stress level, PCBs on both rectangular (3"x5") and square board (3"x3") are designed in the same way in terms of BGA component, pad stackup, pad structure and fabricated by the same workshop. To understand the repeatability, the drop tests were repeated in four (4) different test labs. Those test labs belong to different companies and may use different drop testers. But they all use the same drop test parameters (1500G, 1ms).
      The drop test includes two key items: strain measurement and drop cycle to failure. The PCBs with several strain gage attachments were measured for both TVs and repeated for each test lab. Interestingly enough, it is found that the strain values are comparable to each other among the four test labs but the number of drops to failure is spread very differently. This give us a big alarm that drop test results should be interpreted carefully. Further analysis shows that another parameter, energy dissipation or delta V during the drop cycle, plays a key role but has been neglected by the current JEDEC drop test standard. This study has demonstrated that the drop duration is far less critical as compared to the peak acceleration and delta V for defining the damage of the solder joints. To further understand the shape impact of the acceleration pulse, a spectrum response has been analyzed which proves only the peak acceleration and delta V may be considered to determine the severity of a drop test.
      This is a part of JEDEC B111 Task Group work. The participant companies are (in alphabetical order) Aalto University, Amkor, Auburn University, Blackberry, Cisco, Flextronics, Freescale, Hewlett-Packard, Huawei Technologies, Intel, Lamar University, Maxim Integrated, Microsoft, NVIDIA, Qualcomm, Texas Instruments.
  

  Speaker Biography:
  

      Dongji Xie is currently working in NVIDIA in Santa Clara as senior manager for system reliability. He has been working in reliability and manufacturing in the electronics industry from wafer processing, packaging, PCB assembly for more than 20 years. He received his Ph.D. from City University of Hong Kong and Bachelor and Master Degrees both from Huazhong University of Science and Technology, China. He has been a committee member for Applied Reliability of ECTC since 2002.

  
  

  ---

  If you are not on our Chapter's regular email distribution list for meeting anouncements, you can easily be added! Place yourself on our email distribution list [or send a request to Paul Wesling.]

  
  

  ---

  SCV Chapter Home Page	How to Join IEEE	Contact our Chapter Chair
  CPMT Society Home Page	IEEE Home Page	Email to Webmaster

  Last updated on