IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:

    Robust 3DIC Package Assembly Process Engineering for High Volume Production
    -- Inderjit Singh, Xilinx Inc.

• Registration at 11:30 AM; Lunch ($5) served from 11:30 - 12:00
• Presentation (no cost) at 12:00 noon
• Please reserve by the end of August 10, so we can provide the food.

Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.

You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make an on-line payment for the lunch.



LOCATION: Biltmore Hotel (a change from our usual TI location)
    2151 Laurelwood Road (at 101), Santa Clara -- click map at right.

OVERVIEW:

    As the size and complexity of designs grows larger, Field Programmable Gate Array (FPGA) based design solutions are becoming more dominant in system designs due to their ability to offer higher logic capacity and more on-chip resources. FPGA-based design solutions that offer higher capacity and higher bandwidth with low latency and power can provide system-level functionality similar to Application Specific Integrated Circuits (ASICs). Stacked-die technology enables high-bandwidth connectivity between the multiple die by providing a significantly large number of connections via microbumps. This interposer-based die stacking approach provides low power and latency, but also adds manufacturing complexity. This talk will summarize some of the key assembly and reliability challenges of 28nm 3DIC products assembled with CoWoS (Chip-On-Wafer-On-Substrate) process. During the initial product ramp stage, most of the failures observed were related to interposer-level assembly processes. Specific patterns were developed to isolate the interconnect failures to single ubumps. Apart from interconnect failures, transistor damage occurred during the 3DIC assembly process causing functional failures which were investigated, analyzed and resolved to demonstrate a high-yielding 3DIC assembly process. To understand the reliability of the 3DIC device, a comprehensive reliability test vehicle was developed. The reliability of the 3DIC device mounted on the board was tested for various high temperature storage and thermal cycling test conditions far beyond JEDEC requirements. The comprehensive test methodology was effective in capturing various failure modes and their interactions. During this presentation an overview of the initial development process, reliability data, and key challenges will be discussed.

Speaker Biography:

    Inderjit Singh received his Bachelor of Applied Science, majoring in Applied Physics from University Science Malaysia. He has 25 years of Assembly, Manufacturing, Package Development, Design, Reliability & Chip to Package interaction experiences. His focus areas have been in the development of interconnect technologies and he is considered an industry expert related to Wirebonding, Flip Chip & 3D packaging. He previously worked at National Semiconductor and NVIDIA for 10 years each and has currently been with Xilinx for the last 5 years as Director of Assembly Engineering, managing Overall Package Assembly and Process Integration & New Product/Package ramping to production.