IEEE/CPMT Lunch Meeting, in the Santa Clara Valley:
Void Formation during Soldering
Presentation Slides: "Void Formation during Soldering" (2 MB PDF)
-- Watson Tseng, General Manager, Shenmao America Inc.
Thursday, September 24, 2015
- Registration at 11:30 AM; Lunch ($5; free for IEEE Members with code IEEE2015) served from 11:30 - 12:00
- Presentation (no cost) at 12:00 noon
- Please reserve by the end of September 22, so we can provide the food.
Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.
You may register yourself, plus others from your company/institution, for this lunch and presentation. Please make an on-line payment for the lunch.
LOCATION: Texas Instruments Building E Conference Center
2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.
Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. With decreasing joint sizes, voiding in solder is a leading cause of early failures, such as fatigue and low drop test resistance. The formation of voids in soldering processes including SMT assembly and advanced fine pitch flip chip packaging will be presented. Root causes contributing to void formation are identified and classified. An in-situ observation during reflow is used to reveal the formation mechanism. Materials and process solutions to prevent void formation are suggested in this talk.
- Speaker Biography:
Watson Tseng is General Manager of Shenmao America Inc. He worked in the Shenmao Micro Material Institute for 6 years as a group leader in charge of solder paste development. He has 14 years of experience in failure analysis of SMT and packaging applications. Watson received his M.S. in Chemical Engineering from National Taiwan University.
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