IEEE Santa Clara Valley CPMT Society Chapter, with the SCV Reliability Chapter
"Chips 'Face-Up' Panelization Approach for Fan-Out Packaging"
Presentation Slides: "Chips 'Face-Up' Panelization Approach for Fan-Out Packaging" (1 MB PDF)
Boyd Rogers, Deca Technologies, Inc.
Wednesday, October 14, 2015
- Optional lunch provided ($5 for IEEE members, all students, all unemployed; $10 for non-members)
- For lunch, please bring a $5 or $10 bill
- Registration and (optional lunch) at 11:30 AM
- Presentation (no cost) at 12:00 noon (come at 11:45 AM)
- Please reserve by the end of October 12, so we can provide the food.
PLEASE RESERVE IN ADVANCE --
Please register in advance for this event, using our CPMT Chapter's EventBrite registration site.
You may register yourself, plus others from your company/institution, for both light lunch and presentation, or for only the presentation. Please make an on-line payment for the lunch.
Texas Instruments Building E Conference Center
- For networking/food and/or meeting: at the EventBrite link above.
- Even if you're coming only for the presentation, we want you to sign up on our registration web site, so we can quicken the sign-in process and get everyone seated by noon.
2900 Semiconductor Dr. (off Kifer Rd), Santa Clara -- click map at right.
Fan-Out Wafer-Level Packaging (FOWLP) is poised to become a mainstream packaging technology, providing a means of packaging semiconductor chips with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP), while delivering size and performance benefits similar to WLCSPs. FOWLP can also be used for multi-chip integration to create system-in-packages and thus can compete in applications previously targeted for 2.5D. These benefits have led many in the industry to predict a significant compound annual growth rate for FOWLP over the next few years. Challenges that remain with this technology include developing the infrastructure necessary to support growing industry demand, controlling costs, driving higher yields, and developing smaller linewidths to support high density wiring applications.
This talk describes a unique chips "face-up" approach to panelization, the process in which die are embedded in mold compound to effectively grow the die surface and to create a panel for supporting RDL build-up. In this approach, die with preformed Cu studs are placed face-up on a carrier, using a high-speed pick and place tool to achieve high throughput and low cost. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs, which provide current pathways from the chip IOs to the mold compound surface. A high-speed optical scanner is used to inspect the Cu studs protruding through the mold compound, to determine the actual position of every die on the panel. This information is fed into a proprietary design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. The result is a panelization process which can deliver high yielding panels with high throughput and low cost and with a planar surface capable of supporting high-density RDL wiring.
This presentation details challenges and benefits of this chips face-up approach and describes Adaptive Patterning strategies used to compensate for die displacement in the molded panel and thus achieve high panel yield.
- Speaker Biography:
Boyd Rogers serves as Vice President of Research and Development for Deca Technologies, where he has been a member of the staff since July 2010. Prior to joining Deca, Boyd was VP of Advanced Product Development for Bump and WLCSP at Amkor Technology. He became a member of Amkor through the acquisition of Unitive Electronics in 2004. At Unitive, Boyd worked with other senior staff in managing development of Unitive's polyimide-based WLCSP technology and Unitive's SnAg electroplating technology.
In the 1990's, Boyd held positions at the Dow Chemical Company, developing processing guidelines for Photo-BCB, and at the MCNC Center for Microelectronics, where he worked on multilevel metallization for backend chip fabrication. Boyd holds a Doctorate in Electrical Engineering from Duke University, holds several industry patents and has more than 20 technical white papers published.
Boyd will be discussing Deca's M-Series technology, a unique chips face-up approach to fan-out packaging.
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